1 //***************************************************************************** 2 // 3 // hw_i2s.h - Macros for use in accessing the I2S registers. 4 // 5 // Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_I2S_H__ 26 #define __HW_I2S_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the Inter-Integrated Circuit Sound register 31 // offsets. 32 // 33 //***************************************************************************** 34 #define I2S_O_TXFIFO 0x00000000 // I2S Transmit FIFO Data 35 #define I2S_O_TXFIFOCFG 0x00000004 // I2S Transmit FIFO Configuration 36 #define I2S_O_TXCFG 0x00000008 // I2S Transmit Module 37 // Configuration 38 #define I2S_O_TXLIMIT 0x0000000C // I2S Transmit FIFO Limit 39 #define I2S_O_TXISM 0x00000010 // I2S Transmit Interrupt Status 40 // and Mask 41 #define I2S_O_TXLEV 0x00000018 // I2S Transmit FIFO Level 42 #define I2S_O_RXFIFO 0x00000800 // I2S Receive FIFO Data 43 #define I2S_O_RXFIFOCFG 0x00000804 // I2S Receive FIFO Configuration 44 #define I2S_O_RXCFG 0x00000808 // I2S Receive Module Configuration 45 #define I2S_O_RXLIMIT 0x0000080C // I2S Receive FIFO Limit 46 #define I2S_O_RXISM 0x00000810 // I2S Receive Interrupt Status and 47 // Mask 48 #define I2S_O_RXLEV 0x00000818 // I2S Receive FIFO Level 49 #define I2S_O_CFG 0x00000C00 // I2S Module Configuration 50 #define I2S_O_IM 0x00000C10 // I2S Interrupt Mask 51 #define I2S_O_RIS 0x00000C14 // I2S Raw Interrupt Status 52 #define I2S_O_MIS 0x00000C18 // I2S Masked Interrupt Status 53 #define I2S_O_IC 0x00000C1C // I2S Interrupt Clear 54 55 //***************************************************************************** 56 // 57 // The following are defines for the bit fields in the I2S_O_TXFIFO register. 58 // 59 //***************************************************************************** 60 #define I2S_TXFIFO_M 0xFFFFFFFF // TX Data 61 #define I2S_TXFIFO_S 0 62 63 //***************************************************************************** 64 // 65 // The following are defines for the bit fields in the I2S_O_TXFIFOCFG 66 // register. 67 // 68 //***************************************************************************** 69 #define I2S_TXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size 70 #define I2S_TXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator 71 72 //***************************************************************************** 73 // 74 // The following are defines for the bit fields in the I2S_O_TXCFG register. 75 // 76 //***************************************************************************** 77 #define I2S_TXCFG_JST 0x20000000 // Justification of Output Data 78 #define I2S_TXCFG_DLY 0x10000000 // Data Delay 79 #define I2S_TXCFG_SCP 0x08000000 // SCLK Polarity 80 #define I2S_TXCFG_LRP 0x04000000 // Left/Right Clock Polarity 81 #define I2S_TXCFG_WM_M 0x03000000 // Write Mode 82 #define I2S_TXCFG_WM_DUAL 0x00000000 // Stereo mode 83 #define I2S_TXCFG_WM_COMPACT 0x01000000 // Compact Stereo mode 84 #define I2S_TXCFG_WM_MONO 0x02000000 // Mono mode 85 #define I2S_TXCFG_FMT 0x00800000 // FIFO Empty 86 #define I2S_TXCFG_MSL 0x00400000 // SCLK Master/Slave 87 #define I2S_TXCFG_SSZ_M 0x0000FC00 // Sample Size 88 #define I2S_TXCFG_SDSZ_M 0x000003F0 // System Data Size 89 #define I2S_TXCFG_SSZ_S 10 90 #define I2S_TXCFG_SDSZ_S 4 91 92 //***************************************************************************** 93 // 94 // The following are defines for the bit fields in the I2S_O_TXLIMIT register. 95 // 96 //***************************************************************************** 97 #define I2S_TXLIMIT_LIMIT_M 0x0000001F // FIFO Limit 98 #define I2S_TXLIMIT_LIMIT_S 0 99 100 //***************************************************************************** 101 // 102 // The following are defines for the bit fields in the I2S_O_TXISM register. 103 // 104 //***************************************************************************** 105 #define I2S_TXISM_FFI 0x00010000 // Transmit FIFO Service Request 106 // Interrupt 107 #define I2S_TXISM_FFM 0x00000001 // FIFO Interrupt Mask 108 109 //***************************************************************************** 110 // 111 // The following are defines for the bit fields in the I2S_O_TXLEV register. 112 // 113 //***************************************************************************** 114 #define I2S_TXLEV_LEVEL_M 0x0000001F // Number of Audio Samples 115 #define I2S_TXLEV_LEVEL_S 0 116 117 //***************************************************************************** 118 // 119 // The following are defines for the bit fields in the I2S_O_RXFIFO register. 120 // 121 //***************************************************************************** 122 #define I2S_RXFIFO_M 0xFFFFFFFF // RX Data 123 #define I2S_RXFIFO_S 0 124 125 //***************************************************************************** 126 // 127 // The following are defines for the bit fields in the I2S_O_RXFIFOCFG 128 // register. 129 // 130 //***************************************************************************** 131 #define I2S_RXFIFOCFG_FMM 0x00000004 // FIFO Mono Mode 132 #define I2S_RXFIFOCFG_CSS 0x00000002 // Compact Stereo Sample Size 133 #define I2S_RXFIFOCFG_LRS 0x00000001 // Left-Right Sample Indicator 134 135 //***************************************************************************** 136 // 137 // The following are defines for the bit fields in the I2S_O_RXCFG register. 138 // 139 //***************************************************************************** 140 #define I2S_RXCFG_JST 0x20000000 // Justification of Input Data 141 #define I2S_RXCFG_DLY 0x10000000 // Data Delay 142 #define I2S_RXCFG_SCP 0x08000000 // SCLK Polarity 143 #define I2S_RXCFG_LRP 0x04000000 // Left/Right Clock Polarity 144 #define I2S_RXCFG_RM 0x01000000 // Read Mode 145 #define I2S_RXCFG_MSL 0x00400000 // SCLK Master/Slave 146 #define I2S_RXCFG_SSZ_M 0x0000FC00 // Sample Size 147 #define I2S_RXCFG_SDSZ_M 0x000003F0 // System Data Size 148 #define I2S_RXCFG_SSZ_S 10 149 #define I2S_RXCFG_SDSZ_S 4 150 151 //***************************************************************************** 152 // 153 // The following are defines for the bit fields in the I2S_O_RXLIMIT register. 154 // 155 //***************************************************************************** 156 #define I2S_RXLIMIT_LIMIT_M 0x0000001F // FIFO Limit 157 #define I2S_RXLIMIT_LIMIT_S 0 158 159 //***************************************************************************** 160 // 161 // The following are defines for the bit fields in the I2S_O_RXISM register. 162 // 163 //***************************************************************************** 164 #define I2S_RXISM_FFI 0x00010000 // Receive FIFO Service Request 165 // Interrupt 166 #define I2S_RXISM_FFM 0x00000001 // FIFO Interrupt Mask 167 168 //***************************************************************************** 169 // 170 // The following are defines for the bit fields in the I2S_O_RXLEV register. 171 // 172 //***************************************************************************** 173 #define I2S_RXLEV_LEVEL_M 0x0000001F // Number of Audio Samples 174 #define I2S_RXLEV_LEVEL_S 0 175 176 //***************************************************************************** 177 // 178 // The following are defines for the bit fields in the I2S_O_CFG register. 179 // 180 //***************************************************************************** 181 #define I2S_CFG_RXSLV 0x00000020 // Use External I2S0RXMCLK 182 #define I2S_CFG_TXSLV 0x00000010 // Use External I2S0TXMCLK 183 #define I2S_CFG_RXEN 0x00000002 // Serial Receive Engine Enable 184 #define I2S_CFG_TXEN 0x00000001 // Serial Transmit Engine Enable 185 186 //***************************************************************************** 187 // 188 // The following are defines for the bit fields in the I2S_O_IM register. 189 // 190 //***************************************************************************** 191 #define I2S_IM_RXRE 0x00000020 // Receive FIFO Read Error 192 #define I2S_IM_RXFSR 0x00000010 // Receive FIFO Service Request 193 #define I2S_IM_TXWE 0x00000002 // Transmit FIFO Write Error 194 #define I2S_IM_TXFSR 0x00000001 // Transmit FIFO Service Request 195 196 //***************************************************************************** 197 // 198 // The following are defines for the bit fields in the I2S_O_RIS register. 199 // 200 //***************************************************************************** 201 #define I2S_RIS_RXRE 0x00000020 // Receive FIFO Read Error 202 #define I2S_RIS_RXFSR 0x00000010 // Receive FIFO Service Request 203 #define I2S_RIS_TXWE 0x00000002 // Transmit FIFO Write Error 204 #define I2S_RIS_TXFSR 0x00000001 // Transmit FIFO Service Request 205 206 //***************************************************************************** 207 // 208 // The following are defines for the bit fields in the I2S_O_MIS register. 209 // 210 //***************************************************************************** 211 #define I2S_MIS_RXRE 0x00000020 // Receive FIFO Read Error 212 #define I2S_MIS_RXFSR 0x00000010 // Receive FIFO Service Request 213 #define I2S_MIS_TXWE 0x00000002 // Transmit FIFO Write Error 214 #define I2S_MIS_TXFSR 0x00000001 // Transmit FIFO Service Request 215 216 //***************************************************************************** 217 // 218 // The following are defines for the bit fields in the I2S_O_IC register. 219 // 220 //***************************************************************************** 221 #define I2S_IC_RXRE 0x00000020 // Receive FIFO Read Error 222 #define I2S_IC_TXWE 0x00000002 // Transmit FIFO Write Error 223 224 #endif // __HW_I2S_H__ 225