1 //***************************************************************************** 2 // 3 // hw_nvic.h - Macros used when accessing the NVIC hardware. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_NVIC_H__ 26 #define __HW_NVIC_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the NVIC register addresses. 31 // 32 //***************************************************************************** 33 #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg 34 #define NVIC_ACTLR 0xE000E008 // Auxiliary Control 35 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 36 // Register 37 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 38 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register 39 #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg 40 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 41 #define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable 42 #define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable 43 #define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable 44 #define NVIC_EN4 0xE000E110 // Interrupt 128-131 Set Enable 45 #define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable 46 #define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable 47 #define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable 48 #define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable 49 #define NVIC_DIS4 0xE000E190 // Interrupt 128-131 Clear Enable 50 #define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending 51 #define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending 52 #define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending 53 #define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending 54 #define NVIC_PEND4 0xE000E210 // Interrupt 128-131 Set Pending 55 #define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending 56 #define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending 57 #define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending 58 #define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending 59 #define NVIC_UNPEND4 0xE000E290 // Interrupt 128-131 Clear Pending 60 #define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit 61 #define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit 62 #define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit 63 #define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit 64 #define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-131 Active Bit 65 #define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority 66 #define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority 67 #define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority 68 #define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority 69 #define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority 70 #define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority 71 #define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority 72 #define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority 73 #define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority 74 #define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority 75 #define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority 76 #define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority 77 #define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority 78 #define NVIC_PRI13 0xE000E434 // Interrupt 52-53 Priority 79 #define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority 80 #define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority 81 #define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority 82 #define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority 83 #define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority 84 #define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority 85 #define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority 86 #define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority 87 #define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority 88 #define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority 89 #define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority 90 #define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority 91 #define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority 92 #define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority 93 #define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority 94 #define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority 95 #define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority 96 #define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority 97 #define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority 98 #define NVIC_CPUID 0xE000ED00 // CPU ID Base 99 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State 100 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset 101 #define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset 102 // Control 103 #define NVIC_SYS_CTRL 0xE000ED10 // System Control 104 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control 105 #define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 106 #define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 107 #define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 108 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State 109 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status 110 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status 111 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register 112 #define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address 113 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address 114 #define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control 115 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type 116 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control 117 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number 118 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address 119 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size 120 #define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 121 #define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size 122 // Alias 1 123 #define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 124 #define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size 125 // Alias 2 126 #define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 127 #define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size 128 // Alias 3 129 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg 130 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select 131 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data 132 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control 133 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt 134 #define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control 135 #define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address 136 #define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status 137 // Control 138 139 //***************************************************************************** 140 // 141 // The following are defines for the bit fields in the NVIC_INT_TYPE register. 142 // 143 //***************************************************************************** 144 #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) 145 #define NVIC_INT_TYPE_LINES_S 0 146 147 //***************************************************************************** 148 // 149 // The following are defines for the bit fields in the NVIC_ACTLR register. 150 // 151 //***************************************************************************** 152 #define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating 153 // Point 154 #define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL 155 #define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding 156 #define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer 157 #define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple 158 // Cycle Instructions 159 160 //***************************************************************************** 161 // 162 // The following are defines for the bit fields in the NVIC_ST_CTRL register. 163 // 164 //***************************************************************************** 165 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 166 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 167 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 168 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 169 170 //***************************************************************************** 171 // 172 // The following are defines for the bit fields in the NVIC_ST_RELOAD register. 173 // 174 //***************************************************************************** 175 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value 176 #define NVIC_ST_RELOAD_S 0 177 178 //***************************************************************************** 179 // 180 // The following are defines for the bit fields in the NVIC_ST_CURRENT 181 // register. 182 // 183 //***************************************************************************** 184 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value 185 #define NVIC_ST_CURRENT_S 0 186 187 //***************************************************************************** 188 // 189 // The following are defines for the bit fields in the NVIC_ST_CAL register. 190 // 191 //***************************************************************************** 192 #define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock 193 #define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew 194 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value 195 #define NVIC_ST_CAL_ONEMS_S 0 196 197 //***************************************************************************** 198 // 199 // The following are defines for the bit fields in the NVIC_EN0 register. 200 // 201 //***************************************************************************** 202 #define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable 203 #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable 204 #define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable 205 #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable 206 #define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable 207 #define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable 208 #define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable 209 #define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable 210 #define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable 211 #define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable 212 #define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable 213 #define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable 214 #define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable 215 #define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable 216 #define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable 217 #define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable 218 #define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable 219 #define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable 220 #define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable 221 #define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable 222 #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable 223 #define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable 224 #define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable 225 #define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable 226 #define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable 227 #define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable 228 #define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable 229 #define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable 230 #define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable 231 #define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable 232 #define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable 233 #define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable 234 #define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable 235 236 //***************************************************************************** 237 // 238 // The following are defines for the bit fields in the NVIC_EN1 register. 239 // 240 //***************************************************************************** 241 #define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable 242 #define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable 243 #define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable 244 #define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable 245 #define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable 246 #define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable 247 #define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable 248 #define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable 249 #define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable 250 #define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable 251 #define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable 252 #define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable 253 #define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable 254 #define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable 255 #define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable 256 #define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable 257 #define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable 258 #define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable 259 #define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable 260 #define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable 261 #define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable 262 #define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable 263 #define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable 264 #define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable 265 266 //***************************************************************************** 267 // 268 // The following are defines for the bit fields in the NVIC_EN2 register. 269 // 270 //***************************************************************************** 271 #define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable 272 273 //***************************************************************************** 274 // 275 // The following are defines for the bit fields in the NVIC_EN3 register. 276 // 277 //***************************************************************************** 278 #define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable 279 280 //***************************************************************************** 281 // 282 // The following are defines for the bit fields in the NVIC_EN4 register. 283 // 284 //***************************************************************************** 285 #define NVIC_EN4_INT_M 0x0000000F // Interrupt Enable 286 287 //***************************************************************************** 288 // 289 // The following are defines for the bit fields in the NVIC_DIS0 register. 290 // 291 //***************************************************************************** 292 #define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable 293 #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable 294 #define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable 295 #define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable 296 #define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable 297 #define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable 298 #define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable 299 #define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable 300 #define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable 301 #define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable 302 #define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable 303 #define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable 304 #define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable 305 #define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable 306 #define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable 307 #define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable 308 #define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable 309 #define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable 310 #define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable 311 #define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable 312 #define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable 313 #define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable 314 #define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable 315 #define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable 316 #define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable 317 #define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable 318 #define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable 319 #define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable 320 #define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable 321 #define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable 322 #define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable 323 #define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable 324 #define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable 325 326 //***************************************************************************** 327 // 328 // The following are defines for the bit fields in the NVIC_DIS1 register. 329 // 330 //***************************************************************************** 331 #define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable 332 #define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable 333 #define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable 334 #define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable 335 #define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable 336 #define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable 337 #define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable 338 #define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable 339 #define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable 340 #define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable 341 #define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable 342 #define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable 343 #define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable 344 #define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable 345 #define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable 346 #define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable 347 #define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable 348 #define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable 349 #define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable 350 #define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable 351 #define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable 352 #define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable 353 #define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable 354 #define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable 355 #define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable 356 357 //***************************************************************************** 358 // 359 // The following are defines for the bit fields in the NVIC_DIS2 register. 360 // 361 //***************************************************************************** 362 #define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable 363 364 //***************************************************************************** 365 // 366 // The following are defines for the bit fields in the NVIC_DIS3 register. 367 // 368 //***************************************************************************** 369 #define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable 370 371 //***************************************************************************** 372 // 373 // The following are defines for the bit fields in the NVIC_DIS4 register. 374 // 375 //***************************************************************************** 376 #define NVIC_DIS4_INT_M 0x0000000F // Interrupt Disable 377 378 //***************************************************************************** 379 // 380 // The following are defines for the bit fields in the NVIC_PEND0 register. 381 // 382 //***************************************************************************** 383 #define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending 384 #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend 385 #define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend 386 #define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend 387 #define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend 388 #define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend 389 #define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend 390 #define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend 391 #define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend 392 #define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend 393 #define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend 394 #define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend 395 #define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend 396 #define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend 397 #define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend 398 #define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend 399 #define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend 400 #define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend 401 #define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend 402 #define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend 403 #define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend 404 #define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend 405 #define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend 406 #define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend 407 #define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend 408 #define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend 409 #define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend 410 #define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend 411 #define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend 412 #define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend 413 #define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend 414 #define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend 415 #define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend 416 417 //***************************************************************************** 418 // 419 // The following are defines for the bit fields in the NVIC_PEND1 register. 420 // 421 //***************************************************************************** 422 #define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending 423 #define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend 424 #define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend 425 #define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend 426 #define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend 427 #define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend 428 #define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend 429 #define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend 430 #define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend 431 #define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend 432 #define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend 433 #define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend 434 #define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend 435 #define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend 436 #define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend 437 #define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend 438 #define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend 439 #define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend 440 #define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend 441 #define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend 442 #define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend 443 #define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend 444 #define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend 445 #define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend 446 #define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend 447 448 //***************************************************************************** 449 // 450 // The following are defines for the bit fields in the NVIC_PEND2 register. 451 // 452 //***************************************************************************** 453 #define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending 454 455 //***************************************************************************** 456 // 457 // The following are defines for the bit fields in the NVIC_PEND3 register. 458 // 459 //***************************************************************************** 460 #define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending 461 462 //***************************************************************************** 463 // 464 // The following are defines for the bit fields in the NVIC_PEND4 register. 465 // 466 //***************************************************************************** 467 #define NVIC_PEND4_INT_M 0x0000000F // Interrupt Set Pending 468 469 //***************************************************************************** 470 // 471 // The following are defines for the bit fields in the NVIC_UNPEND0 register. 472 // 473 //***************************************************************************** 474 #define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending 475 #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend 476 #define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend 477 #define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend 478 #define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend 479 #define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend 480 #define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend 481 #define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend 482 #define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend 483 #define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend 484 #define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend 485 #define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend 486 #define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend 487 #define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend 488 #define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend 489 #define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend 490 #define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend 491 #define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend 492 #define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend 493 #define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend 494 #define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend 495 #define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend 496 #define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend 497 #define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend 498 #define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend 499 #define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend 500 #define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend 501 #define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend 502 #define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend 503 #define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend 504 #define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend 505 #define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend 506 #define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend 507 508 //***************************************************************************** 509 // 510 // The following are defines for the bit fields in the NVIC_UNPEND1 register. 511 // 512 //***************************************************************************** 513 #define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending 514 #define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend 515 #define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend 516 #define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend 517 #define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend 518 #define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend 519 #define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend 520 #define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend 521 #define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend 522 #define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend 523 #define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend 524 #define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend 525 #define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend 526 #define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend 527 #define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend 528 #define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend 529 #define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend 530 #define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend 531 #define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend 532 #define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend 533 #define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend 534 #define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend 535 #define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend 536 #define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend 537 #define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend 538 539 //***************************************************************************** 540 // 541 // The following are defines for the bit fields in the NVIC_UNPEND2 register. 542 // 543 //***************************************************************************** 544 #define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending 545 546 //***************************************************************************** 547 // 548 // The following are defines for the bit fields in the NVIC_UNPEND3 register. 549 // 550 //***************************************************************************** 551 #define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending 552 553 //***************************************************************************** 554 // 555 // The following are defines for the bit fields in the NVIC_UNPEND4 register. 556 // 557 //***************************************************************************** 558 #define NVIC_UNPEND4_INT_M 0x0000000F // Interrupt Clear Pending 559 560 //***************************************************************************** 561 // 562 // The following are defines for the bit fields in the NVIC_ACTIVE0 register. 563 // 564 //***************************************************************************** 565 #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active 566 #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active 567 #define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active 568 #define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active 569 #define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active 570 #define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active 571 #define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active 572 #define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active 573 #define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active 574 #define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active 575 #define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active 576 #define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active 577 #define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active 578 #define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active 579 #define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active 580 #define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active 581 #define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active 582 #define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active 583 #define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active 584 #define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active 585 #define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active 586 #define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active 587 #define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active 588 #define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active 589 #define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active 590 #define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active 591 #define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active 592 #define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active 593 #define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active 594 #define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active 595 #define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active 596 #define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active 597 #define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active 598 599 //***************************************************************************** 600 // 601 // The following are defines for the bit fields in the NVIC_ACTIVE1 register. 602 // 603 //***************************************************************************** 604 #define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active 605 #define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active 606 #define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active 607 #define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active 608 #define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active 609 #define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active 610 #define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active 611 #define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active 612 #define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active 613 #define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active 614 #define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active 615 #define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active 616 #define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active 617 #define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active 618 #define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active 619 #define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active 620 #define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active 621 #define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active 622 #define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active 623 #define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active 624 #define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active 625 #define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active 626 #define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active 627 #define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active 628 #define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active 629 630 //***************************************************************************** 631 // 632 // The following are defines for the bit fields in the NVIC_ACTIVE2 register. 633 // 634 //***************************************************************************** 635 #define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active 636 637 //***************************************************************************** 638 // 639 // The following are defines for the bit fields in the NVIC_ACTIVE3 register. 640 // 641 //***************************************************************************** 642 #define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active 643 644 //***************************************************************************** 645 // 646 // The following are defines for the bit fields in the NVIC_ACTIVE4 register. 647 // 648 //***************************************************************************** 649 #define NVIC_ACTIVE4_INT_M 0x0000000F // Interrupt Active 650 651 //***************************************************************************** 652 // 653 // The following are defines for the bit fields in the NVIC_PRI0 register. 654 // 655 //***************************************************************************** 656 #define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask 657 #define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask 658 #define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask 659 #define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask 660 #define NVIC_PRI0_INT3_S 29 661 #define NVIC_PRI0_INT2_S 21 662 #define NVIC_PRI0_INT1_S 13 663 #define NVIC_PRI0_INT0_S 5 664 665 //***************************************************************************** 666 // 667 // The following are defines for the bit fields in the NVIC_PRI1 register. 668 // 669 //***************************************************************************** 670 #define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask 671 #define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask 672 #define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask 673 #define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask 674 #define NVIC_PRI1_INT7_S 29 675 #define NVIC_PRI1_INT6_S 21 676 #define NVIC_PRI1_INT5_S 13 677 #define NVIC_PRI1_INT4_S 5 678 679 //***************************************************************************** 680 // 681 // The following are defines for the bit fields in the NVIC_PRI2 register. 682 // 683 //***************************************************************************** 684 #define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask 685 #define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask 686 #define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask 687 #define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask 688 #define NVIC_PRI2_INT11_S 29 689 #define NVIC_PRI2_INT10_S 21 690 #define NVIC_PRI2_INT9_S 13 691 #define NVIC_PRI2_INT8_S 5 692 693 //***************************************************************************** 694 // 695 // The following are defines for the bit fields in the NVIC_PRI3 register. 696 // 697 //***************************************************************************** 698 #define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask 699 #define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask 700 #define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask 701 #define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask 702 #define NVIC_PRI3_INT15_S 29 703 #define NVIC_PRI3_INT14_S 21 704 #define NVIC_PRI3_INT13_S 13 705 #define NVIC_PRI3_INT12_S 5 706 707 //***************************************************************************** 708 // 709 // The following are defines for the bit fields in the NVIC_PRI4 register. 710 // 711 //***************************************************************************** 712 #define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask 713 #define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask 714 #define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask 715 #define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask 716 #define NVIC_PRI4_INT19_S 29 717 #define NVIC_PRI4_INT18_S 21 718 #define NVIC_PRI4_INT17_S 13 719 #define NVIC_PRI4_INT16_S 5 720 721 //***************************************************************************** 722 // 723 // The following are defines for the bit fields in the NVIC_PRI5 register. 724 // 725 //***************************************************************************** 726 #define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask 727 #define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask 728 #define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask 729 #define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask 730 #define NVIC_PRI5_INT23_S 29 731 #define NVIC_PRI5_INT22_S 21 732 #define NVIC_PRI5_INT21_S 13 733 #define NVIC_PRI5_INT20_S 5 734 735 //***************************************************************************** 736 // 737 // The following are defines for the bit fields in the NVIC_PRI6 register. 738 // 739 //***************************************************************************** 740 #define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask 741 #define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask 742 #define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask 743 #define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask 744 #define NVIC_PRI6_INT27_S 29 745 #define NVIC_PRI6_INT26_S 21 746 #define NVIC_PRI6_INT25_S 13 747 #define NVIC_PRI6_INT24_S 5 748 749 //***************************************************************************** 750 // 751 // The following are defines for the bit fields in the NVIC_PRI7 register. 752 // 753 //***************************************************************************** 754 #define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask 755 #define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask 756 #define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask 757 #define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask 758 #define NVIC_PRI7_INT31_S 29 759 #define NVIC_PRI7_INT30_S 21 760 #define NVIC_PRI7_INT29_S 13 761 #define NVIC_PRI7_INT28_S 5 762 763 //***************************************************************************** 764 // 765 // The following are defines for the bit fields in the NVIC_PRI8 register. 766 // 767 //***************************************************************************** 768 #define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask 769 #define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask 770 #define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask 771 #define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask 772 #define NVIC_PRI8_INT35_S 29 773 #define NVIC_PRI8_INT34_S 21 774 #define NVIC_PRI8_INT33_S 13 775 #define NVIC_PRI8_INT32_S 5 776 777 //***************************************************************************** 778 // 779 // The following are defines for the bit fields in the NVIC_PRI9 register. 780 // 781 //***************************************************************************** 782 #define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask 783 #define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask 784 #define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask 785 #define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask 786 #define NVIC_PRI9_INT39_S 29 787 #define NVIC_PRI9_INT38_S 21 788 #define NVIC_PRI9_INT37_S 13 789 #define NVIC_PRI9_INT36_S 5 790 791 //***************************************************************************** 792 // 793 // The following are defines for the bit fields in the NVIC_PRI10 register. 794 // 795 //***************************************************************************** 796 #define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask 797 #define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask 798 #define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask 799 #define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask 800 #define NVIC_PRI10_INT43_S 29 801 #define NVIC_PRI10_INT42_S 21 802 #define NVIC_PRI10_INT41_S 13 803 #define NVIC_PRI10_INT40_S 5 804 805 //***************************************************************************** 806 // 807 // The following are defines for the bit fields in the NVIC_PRI11 register. 808 // 809 //***************************************************************************** 810 #define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask 811 #define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask 812 #define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask 813 #define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask 814 #define NVIC_PRI11_INT47_S 29 815 #define NVIC_PRI11_INT46_S 21 816 #define NVIC_PRI11_INT45_S 13 817 #define NVIC_PRI11_INT44_S 5 818 819 //***************************************************************************** 820 // 821 // The following are defines for the bit fields in the NVIC_PRI12 register. 822 // 823 //***************************************************************************** 824 #define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask 825 #define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask 826 #define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask 827 #define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask 828 #define NVIC_PRI12_INT51_S 29 829 #define NVIC_PRI12_INT50_S 21 830 #define NVIC_PRI12_INT49_S 13 831 #define NVIC_PRI12_INT48_S 5 832 833 //***************************************************************************** 834 // 835 // The following are defines for the bit fields in the NVIC_PRI13 register. 836 // 837 //***************************************************************************** 838 #define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask 839 #define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask 840 #define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask 841 #define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask 842 #define NVIC_PRI13_INT55_S 29 843 #define NVIC_PRI13_INT54_S 21 844 #define NVIC_PRI13_INT53_S 13 845 #define NVIC_PRI13_INT52_S 5 846 847 //***************************************************************************** 848 // 849 // The following are defines for the bit fields in the NVIC_PRI14 register. 850 // 851 //***************************************************************************** 852 #define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask 853 #define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask 854 #define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask 855 #define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask 856 #define NVIC_PRI14_INTD_S 29 857 #define NVIC_PRI14_INTC_S 21 858 #define NVIC_PRI14_INTB_S 13 859 #define NVIC_PRI14_INTA_S 5 860 861 //***************************************************************************** 862 // 863 // The following are defines for the bit fields in the NVIC_PRI15 register. 864 // 865 //***************************************************************************** 866 #define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask 867 #define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask 868 #define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask 869 #define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask 870 #define NVIC_PRI15_INTD_S 29 871 #define NVIC_PRI15_INTC_S 21 872 #define NVIC_PRI15_INTB_S 13 873 #define NVIC_PRI15_INTA_S 5 874 875 //***************************************************************************** 876 // 877 // The following are defines for the bit fields in the NVIC_PRI16 register. 878 // 879 //***************************************************************************** 880 #define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask 881 #define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask 882 #define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask 883 #define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask 884 #define NVIC_PRI16_INTD_S 29 885 #define NVIC_PRI16_INTC_S 21 886 #define NVIC_PRI16_INTB_S 13 887 #define NVIC_PRI16_INTA_S 5 888 889 //***************************************************************************** 890 // 891 // The following are defines for the bit fields in the NVIC_PRI17 register. 892 // 893 //***************************************************************************** 894 #define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask 895 #define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask 896 #define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask 897 #define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask 898 #define NVIC_PRI17_INTD_S 29 899 #define NVIC_PRI17_INTC_S 21 900 #define NVIC_PRI17_INTB_S 13 901 #define NVIC_PRI17_INTA_S 5 902 903 //***************************************************************************** 904 // 905 // The following are defines for the bit fields in the NVIC_PRI18 register. 906 // 907 //***************************************************************************** 908 #define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask 909 #define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask 910 #define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask 911 #define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask 912 #define NVIC_PRI18_INTD_S 29 913 #define NVIC_PRI18_INTC_S 21 914 #define NVIC_PRI18_INTB_S 13 915 #define NVIC_PRI18_INTA_S 5 916 917 //***************************************************************************** 918 // 919 // The following are defines for the bit fields in the NVIC_PRI19 register. 920 // 921 //***************************************************************************** 922 #define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask 923 #define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask 924 #define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask 925 #define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask 926 #define NVIC_PRI19_INTD_S 29 927 #define NVIC_PRI19_INTC_S 21 928 #define NVIC_PRI19_INTB_S 13 929 #define NVIC_PRI19_INTA_S 5 930 931 //***************************************************************************** 932 // 933 // The following are defines for the bit fields in the NVIC_PRI20 register. 934 // 935 //***************************************************************************** 936 #define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask 937 #define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask 938 #define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask 939 #define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask 940 #define NVIC_PRI20_INTD_S 29 941 #define NVIC_PRI20_INTC_S 21 942 #define NVIC_PRI20_INTB_S 13 943 #define NVIC_PRI20_INTA_S 5 944 945 //***************************************************************************** 946 // 947 // The following are defines for the bit fields in the NVIC_PRI21 register. 948 // 949 //***************************************************************************** 950 #define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask 951 #define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask 952 #define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask 953 #define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask 954 #define NVIC_PRI21_INTD_S 29 955 #define NVIC_PRI21_INTC_S 21 956 #define NVIC_PRI21_INTB_S 13 957 #define NVIC_PRI21_INTA_S 5 958 959 //***************************************************************************** 960 // 961 // The following are defines for the bit fields in the NVIC_PRI22 register. 962 // 963 //***************************************************************************** 964 #define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask 965 #define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask 966 #define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask 967 #define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask 968 #define NVIC_PRI22_INTD_S 29 969 #define NVIC_PRI22_INTC_S 21 970 #define NVIC_PRI22_INTB_S 13 971 #define NVIC_PRI22_INTA_S 5 972 973 //***************************************************************************** 974 // 975 // The following are defines for the bit fields in the NVIC_PRI23 register. 976 // 977 //***************************************************************************** 978 #define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask 979 #define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask 980 #define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask 981 #define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask 982 #define NVIC_PRI23_INTD_S 29 983 #define NVIC_PRI23_INTC_S 21 984 #define NVIC_PRI23_INTB_S 13 985 #define NVIC_PRI23_INTA_S 5 986 987 //***************************************************************************** 988 // 989 // The following are defines for the bit fields in the NVIC_PRI24 register. 990 // 991 //***************************************************************************** 992 #define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask 993 #define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask 994 #define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask 995 #define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask 996 #define NVIC_PRI24_INTD_S 29 997 #define NVIC_PRI24_INTC_S 21 998 #define NVIC_PRI24_INTB_S 13 999 #define NVIC_PRI24_INTA_S 5 1000 1001 //***************************************************************************** 1002 // 1003 // The following are defines for the bit fields in the NVIC_PRI25 register. 1004 // 1005 //***************************************************************************** 1006 #define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask 1007 #define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask 1008 #define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask 1009 #define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask 1010 #define NVIC_PRI25_INTD_S 29 1011 #define NVIC_PRI25_INTC_S 21 1012 #define NVIC_PRI25_INTB_S 13 1013 #define NVIC_PRI25_INTA_S 5 1014 1015 //***************************************************************************** 1016 // 1017 // The following are defines for the bit fields in the NVIC_PRI26 register. 1018 // 1019 //***************************************************************************** 1020 #define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask 1021 #define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask 1022 #define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask 1023 #define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask 1024 #define NVIC_PRI26_INTD_S 29 1025 #define NVIC_PRI26_INTC_S 21 1026 #define NVIC_PRI26_INTB_S 13 1027 #define NVIC_PRI26_INTA_S 5 1028 1029 //***************************************************************************** 1030 // 1031 // The following are defines for the bit fields in the NVIC_PRI27 register. 1032 // 1033 //***************************************************************************** 1034 #define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask 1035 #define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask 1036 #define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask 1037 #define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask 1038 #define NVIC_PRI27_INTD_S 29 1039 #define NVIC_PRI27_INTC_S 21 1040 #define NVIC_PRI27_INTB_S 13 1041 #define NVIC_PRI27_INTA_S 5 1042 1043 //***************************************************************************** 1044 // 1045 // The following are defines for the bit fields in the NVIC_PRI28 register. 1046 // 1047 //***************************************************************************** 1048 #define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask 1049 #define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask 1050 #define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask 1051 #define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask 1052 #define NVIC_PRI28_INTD_S 29 1053 #define NVIC_PRI28_INTC_S 21 1054 #define NVIC_PRI28_INTB_S 13 1055 #define NVIC_PRI28_INTA_S 5 1056 1057 //***************************************************************************** 1058 // 1059 // The following are defines for the bit fields in the NVIC_PRI29 register. 1060 // 1061 //***************************************************************************** 1062 #define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask 1063 #define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask 1064 #define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask 1065 #define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask 1066 #define NVIC_PRI29_INTD_S 29 1067 #define NVIC_PRI29_INTC_S 21 1068 #define NVIC_PRI29_INTB_S 13 1069 #define NVIC_PRI29_INTA_S 5 1070 1071 //***************************************************************************** 1072 // 1073 // The following are defines for the bit fields in the NVIC_PRI30 register. 1074 // 1075 //***************************************************************************** 1076 #define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask 1077 #define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask 1078 #define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask 1079 #define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask 1080 #define NVIC_PRI30_INTD_S 29 1081 #define NVIC_PRI30_INTC_S 21 1082 #define NVIC_PRI30_INTB_S 13 1083 #define NVIC_PRI30_INTA_S 5 1084 1085 //***************************************************************************** 1086 // 1087 // The following are defines for the bit fields in the NVIC_PRI31 register. 1088 // 1089 //***************************************************************************** 1090 #define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask 1091 #define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask 1092 #define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask 1093 #define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask 1094 #define NVIC_PRI31_INTD_S 29 1095 #define NVIC_PRI31_INTC_S 21 1096 #define NVIC_PRI31_INTB_S 13 1097 #define NVIC_PRI31_INTA_S 5 1098 1099 //***************************************************************************** 1100 // 1101 // The following are defines for the bit fields in the NVIC_PRI32 register. 1102 // 1103 //***************************************************************************** 1104 #define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask 1105 #define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask 1106 #define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask 1107 #define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask 1108 #define NVIC_PRI32_INTD_S 29 1109 #define NVIC_PRI32_INTC_S 21 1110 #define NVIC_PRI32_INTB_S 13 1111 #define NVIC_PRI32_INTA_S 5 1112 1113 //***************************************************************************** 1114 // 1115 // The following are defines for the bit fields in the NVIC_CPUID register. 1116 // 1117 //***************************************************************************** 1118 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code 1119 #define NVIC_CPUID_IMP_ARM 0x41000000 // ARM 1120 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number 1121 #define NVIC_CPUID_CON_M 0x000F0000 // Constant 1122 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number 1123 #define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor 1124 #define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor 1125 #define NVIC_CPUID_REV_M 0x0000000F // Revision Number 1126 1127 //***************************************************************************** 1128 // 1129 // The following are defines for the bit fields in the NVIC_INT_CTRL register. 1130 // 1131 //***************************************************************************** 1132 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending 1133 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending 1134 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending 1135 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending 1136 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending 1137 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling 1138 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending 1139 #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number 1140 #define NVIC_INT_CTRL_VEC_PEN_NMI \ 1141 0x00002000 // NMI 1142 #define NVIC_INT_CTRL_VEC_PEN_HARD \ 1143 0x00003000 // Hard fault 1144 #define NVIC_INT_CTRL_VEC_PEN_MEM \ 1145 0x00004000 // Memory management fault 1146 #define NVIC_INT_CTRL_VEC_PEN_BUS \ 1147 0x00005000 // Bus fault 1148 #define NVIC_INT_CTRL_VEC_PEN_USG \ 1149 0x00006000 // Usage fault 1150 #define NVIC_INT_CTRL_VEC_PEN_SVC \ 1151 0x0000B000 // SVCall 1152 #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ 1153 0x0000E000 // PendSV 1154 #define NVIC_INT_CTRL_VEC_PEN_TICK \ 1155 0x0000F000 // SysTick 1156 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base 1157 #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number 1158 #define NVIC_INT_CTRL_VEC_PEN_S 12 1159 #define NVIC_INT_CTRL_VEC_ACT_S 0 1160 1161 //***************************************************************************** 1162 // 1163 // The following are defines for the bit fields in the NVIC_VTABLE register. 1164 // 1165 //***************************************************************************** 1166 #define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base 1167 #define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset 1168 #define NVIC_VTABLE_OFFSET_S 10 1169 1170 //***************************************************************************** 1171 // 1172 // The following are defines for the bit fields in the NVIC_APINT register. 1173 // 1174 //***************************************************************************** 1175 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key 1176 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key 1177 #define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess 1178 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping 1179 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split 1180 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split 1181 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split 1182 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split 1183 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split 1184 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split 1185 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split 1186 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split 1187 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request 1188 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault 1189 #define NVIC_APINT_VECT_RESET 0x00000001 // System Reset 1190 1191 //***************************************************************************** 1192 // 1193 // The following are defines for the bit fields in the NVIC_SYS_CTRL register. 1194 // 1195 //***************************************************************************** 1196 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending 1197 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable 1198 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit 1199 1200 //***************************************************************************** 1201 // 1202 // The following are defines for the bit fields in the NVIC_CFG_CTRL register. 1203 // 1204 //***************************************************************************** 1205 #define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception 1206 // Entry 1207 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and 1208 // Fault 1209 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 1210 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access 1211 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger 1212 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control 1213 1214 //***************************************************************************** 1215 // 1216 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. 1217 // 1218 //***************************************************************************** 1219 #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority 1220 #define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority 1221 #define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority 1222 #define NVIC_SYS_PRI1_USAGE_S 21 1223 #define NVIC_SYS_PRI1_BUS_S 13 1224 #define NVIC_SYS_PRI1_MEM_S 5 1225 1226 //***************************************************************************** 1227 // 1228 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. 1229 // 1230 //***************************************************************************** 1231 #define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority 1232 #define NVIC_SYS_PRI2_SVC_S 29 1233 1234 //***************************************************************************** 1235 // 1236 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. 1237 // 1238 //***************************************************************************** 1239 #define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority 1240 #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority 1241 #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority 1242 #define NVIC_SYS_PRI3_TICK_S 29 1243 #define NVIC_SYS_PRI3_PENDSV_S 21 1244 #define NVIC_SYS_PRI3_DEBUG_S 5 1245 1246 //***************************************************************************** 1247 // 1248 // The following are defines for the bit fields in the NVIC_SYS_HND_CTRL 1249 // register. 1250 // 1251 //***************************************************************************** 1252 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable 1253 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable 1254 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable 1255 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending 1256 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending 1257 #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending 1258 #define NVIC_SYS_HND_CTRL_USAGEP \ 1259 0x00001000 // Usage Fault Pending 1260 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active 1261 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active 1262 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active 1263 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active 1264 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active 1265 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active 1266 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active 1267 1268 //***************************************************************************** 1269 // 1270 // The following are defines for the bit fields in the NVIC_FAULT_STAT 1271 // register. 1272 // 1273 //***************************************************************************** 1274 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault 1275 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault 1276 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault 1277 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault 1278 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault 1279 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage 1280 // Fault 1281 #define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid 1282 #define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy 1283 // State Preservation 1284 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault 1285 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault 1286 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error 1287 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error 1288 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error 1289 #define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address 1290 // Register Valid 1291 #define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on 1292 // Floating-Point Lazy State 1293 // Preservation 1294 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation 1295 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation 1296 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation 1297 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation 1298 1299 //***************************************************************************** 1300 // 1301 // The following are defines for the bit fields in the NVIC_HFAULT_STAT 1302 // register. 1303 // 1304 //***************************************************************************** 1305 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event 1306 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault 1307 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault 1308 1309 //***************************************************************************** 1310 // 1311 // The following are defines for the bit fields in the NVIC_DEBUG_STAT 1312 // register. 1313 // 1314 //***************************************************************************** 1315 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted 1316 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch 1317 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match 1318 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction 1319 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request 1320 1321 //***************************************************************************** 1322 // 1323 // The following are defines for the bit fields in the NVIC_MM_ADDR register. 1324 // 1325 //***************************************************************************** 1326 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address 1327 #define NVIC_MM_ADDR_S 0 1328 1329 //***************************************************************************** 1330 // 1331 // The following are defines for the bit fields in the NVIC_FAULT_ADDR 1332 // register. 1333 // 1334 //***************************************************************************** 1335 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address 1336 #define NVIC_FAULT_ADDR_S 0 1337 1338 //***************************************************************************** 1339 // 1340 // The following are defines for the bit fields in the NVIC_CPAC register. 1341 // 1342 //***************************************************************************** 1343 #define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access 1344 // Privilege 1345 #define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied 1346 #define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only 1347 #define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access 1348 #define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access 1349 // Privilege 1350 #define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied 1351 #define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only 1352 #define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access 1353 1354 //***************************************************************************** 1355 // 1356 // The following are defines for the bit fields in the NVIC_MPU_TYPE register. 1357 // 1358 //***************************************************************************** 1359 #define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions 1360 #define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions 1361 #define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU 1362 #define NVIC_MPU_TYPE_IREGION_S 16 1363 #define NVIC_MPU_TYPE_DREGION_S 8 1364 1365 //***************************************************************************** 1366 // 1367 // The following are defines for the bit fields in the NVIC_MPU_CTRL register. 1368 // 1369 //***************************************************************************** 1370 #define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region 1371 #define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults 1372 #define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable 1373 1374 //***************************************************************************** 1375 // 1376 // The following are defines for the bit fields in the NVIC_MPU_NUMBER 1377 // register. 1378 // 1379 //***************************************************************************** 1380 #define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access 1381 #define NVIC_MPU_NUMBER_S 0 1382 1383 //***************************************************************************** 1384 // 1385 // The following are defines for the bit fields in the NVIC_MPU_BASE register. 1386 // 1387 //***************************************************************************** 1388 #define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask 1389 #define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid 1390 #define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number 1391 #define NVIC_MPU_BASE_ADDR_S 5 1392 #define NVIC_MPU_BASE_REGION_S 0 1393 1394 //***************************************************************************** 1395 // 1396 // The following are defines for the bit fields in the NVIC_MPU_ATTR register. 1397 // 1398 //***************************************************************************** 1399 #define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes 1400 #define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable 1401 #define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege 1402 #define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access 1403 #define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none 1404 #define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only 1405 #define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw 1406 #define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none 1407 #define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro 1408 #define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask 1409 #define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable 1410 #define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable 1411 #define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable 1412 #define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits 1413 #define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable 1414 #define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable 1415 #define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable 1416 #define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable 1417 #define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable 1418 #define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable 1419 #define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable 1420 #define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable 1421 #define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask 1422 #define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes 1423 #define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes 1424 #define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes 1425 #define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes 1426 #define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes 1427 #define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes 1428 #define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes 1429 #define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes 1430 #define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes 1431 #define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes 1432 #define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes 1433 #define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes 1434 #define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes 1435 #define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes 1436 #define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes 1437 #define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes 1438 #define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes 1439 #define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes 1440 #define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes 1441 #define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes 1442 #define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes 1443 #define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes 1444 #define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes 1445 #define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes 1446 #define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes 1447 #define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes 1448 #define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes 1449 #define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes 1450 #define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable 1451 1452 //***************************************************************************** 1453 // 1454 // The following are defines for the bit fields in the NVIC_MPU_BASE1 register. 1455 // 1456 //***************************************************************************** 1457 #define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask 1458 #define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid 1459 #define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number 1460 #define NVIC_MPU_BASE1_ADDR_S 5 1461 #define NVIC_MPU_BASE1_REGION_S 0 1462 1463 //***************************************************************************** 1464 // 1465 // The following are defines for the bit fields in the NVIC_MPU_ATTR1 register. 1466 // 1467 //***************************************************************************** 1468 #define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable 1469 #define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege 1470 #define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask 1471 #define NVIC_MPU_ATTR1_SHAREABLE \ 1472 0x00040000 // Shareable 1473 #define NVIC_MPU_ATTR1_CACHEABLE \ 1474 0x00020000 // Cacheable 1475 #define NVIC_MPU_ATTR1_BUFFRABLE \ 1476 0x00010000 // Bufferable 1477 #define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits 1478 #define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask 1479 #define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable 1480 1481 //***************************************************************************** 1482 // 1483 // The following are defines for the bit fields in the NVIC_MPU_BASE2 register. 1484 // 1485 //***************************************************************************** 1486 #define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask 1487 #define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid 1488 #define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number 1489 #define NVIC_MPU_BASE2_ADDR_S 5 1490 #define NVIC_MPU_BASE2_REGION_S 0 1491 1492 //***************************************************************************** 1493 // 1494 // The following are defines for the bit fields in the NVIC_MPU_ATTR2 register. 1495 // 1496 //***************************************************************************** 1497 #define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable 1498 #define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege 1499 #define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask 1500 #define NVIC_MPU_ATTR2_SHAREABLE \ 1501 0x00040000 // Shareable 1502 #define NVIC_MPU_ATTR2_CACHEABLE \ 1503 0x00020000 // Cacheable 1504 #define NVIC_MPU_ATTR2_BUFFRABLE \ 1505 0x00010000 // Bufferable 1506 #define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits 1507 #define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask 1508 #define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable 1509 1510 //***************************************************************************** 1511 // 1512 // The following are defines for the bit fields in the NVIC_MPU_BASE3 register. 1513 // 1514 //***************************************************************************** 1515 #define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask 1516 #define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid 1517 #define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number 1518 #define NVIC_MPU_BASE3_ADDR_S 5 1519 #define NVIC_MPU_BASE3_REGION_S 0 1520 1521 //***************************************************************************** 1522 // 1523 // The following are defines for the bit fields in the NVIC_MPU_ATTR3 register. 1524 // 1525 //***************************************************************************** 1526 #define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable 1527 #define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege 1528 #define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask 1529 #define NVIC_MPU_ATTR3_SHAREABLE \ 1530 0x00040000 // Shareable 1531 #define NVIC_MPU_ATTR3_CACHEABLE \ 1532 0x00020000 // Cacheable 1533 #define NVIC_MPU_ATTR3_BUFFRABLE \ 1534 0x00010000 // Bufferable 1535 #define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits 1536 #define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask 1537 #define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable 1538 1539 //***************************************************************************** 1540 // 1541 // The following are defines for the bit fields in the NVIC_DBG_CTRL register. 1542 // 1543 //***************************************************************************** 1544 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask 1545 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key 1546 #define NVIC_DBG_CTRL_S_RESET_ST \ 1547 0x02000000 // Core has reset since last read 1548 #define NVIC_DBG_CTRL_S_RETIRE_ST \ 1549 0x01000000 // Core has executed insruction 1550 // since last read 1551 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up 1552 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping 1553 #define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt 1554 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available 1555 #define NVIC_DBG_CTRL_C_SNAPSTALL \ 1556 0x00000020 // Breaks a stalled load/store 1557 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping 1558 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core 1559 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core 1560 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug 1561 1562 //***************************************************************************** 1563 // 1564 // The following are defines for the bit fields in the NVIC_DBG_XFER register. 1565 // 1566 //***************************************************************************** 1567 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read 1568 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register 1569 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 1570 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 1571 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 1572 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 1573 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 1574 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 1575 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 1576 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 1577 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 1578 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 1579 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 1580 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 1581 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 1582 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 1583 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 1584 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 1585 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register 1586 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP 1587 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP 1588 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP 1589 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask 1590 1591 //***************************************************************************** 1592 // 1593 // The following are defines for the bit fields in the NVIC_DBG_DATA register. 1594 // 1595 //***************************************************************************** 1596 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache 1597 #define NVIC_DBG_DATA_S 0 1598 1599 //***************************************************************************** 1600 // 1601 // The following are defines for the bit fields in the NVIC_DBG_INT register. 1602 // 1603 //***************************************************************************** 1604 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault 1605 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors 1606 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error 1607 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state 1608 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check 1609 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error 1610 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault 1611 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status 1612 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset 1613 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending 1614 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch 1615 1616 //***************************************************************************** 1617 // 1618 // The following are defines for the bit fields in the NVIC_SW_TRIG register. 1619 // 1620 //***************************************************************************** 1621 #define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID 1622 #define NVIC_SW_TRIG_INTID_S 0 1623 1624 //***************************************************************************** 1625 // 1626 // The following are defines for the bit fields in the NVIC_FPCC register. 1627 // 1628 //***************************************************************************** 1629 #define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation 1630 // Enable 1631 #define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable 1632 #define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready 1633 #define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready 1634 #define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready 1635 #define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready 1636 #define NVIC_FPCC_THREAD 0x00000008 // Thread Mode 1637 #define NVIC_FPCC_USER 0x00000002 // User Privilege Level 1638 #define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active 1639 1640 //***************************************************************************** 1641 // 1642 // The following are defines for the bit fields in the NVIC_FPCA register. 1643 // 1644 //***************************************************************************** 1645 #define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address 1646 #define NVIC_FPCA_ADDRESS_S 3 1647 1648 //***************************************************************************** 1649 // 1650 // The following are defines for the bit fields in the NVIC_FPDSC register. 1651 // 1652 //***************************************************************************** 1653 #define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default 1654 #define NVIC_FPDSC_DN 0x02000000 // DN Bit Default 1655 #define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default 1656 #define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default 1657 #define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode 1658 #define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP) 1659 // mode 1660 #define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity 1661 // (RM) mode 1662 #define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode 1663 1664 #endif // __HW_NVIC_H__ 1665