1 //***************************************************************************** 2 // 3 // hw_ssi.h - Macros used when accessing the SSI hardware. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_SSI_H__ 26 #define __HW_SSI_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the SSI register offsets. 31 // 32 //***************************************************************************** 33 #define SSI_O_CR0 0x00000000 // SSI Control 0 34 #define SSI_O_CR1 0x00000004 // SSI Control 1 35 #define SSI_O_DR 0x00000008 // SSI Data 36 #define SSI_O_SR 0x0000000C // SSI Status 37 #define SSI_O_CPSR 0x00000010 // SSI Clock Prescale 38 #define SSI_O_IM 0x00000014 // SSI Interrupt Mask 39 #define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status 40 #define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status 41 #define SSI_O_ICR 0x00000020 // SSI Interrupt Clear 42 #define SSI_O_DMACTL 0x00000024 // SSI DMA Control 43 #define SSI_O_CC 0x00000FC8 // SSI Clock Configuration 44 45 //***************************************************************************** 46 // 47 // The following are defines for the bit fields in the SSI_O_CR0 register. 48 // 49 //***************************************************************************** 50 #define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate 51 #define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase 52 #define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity 53 #define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select 54 #define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format 55 #define SSI_CR0_FRF_TI 0x00000010 // Texas Instruments Synchronous 56 // Serial Frame Format 57 #define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format 58 #define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select 59 #define SSI_CR0_DSS_4 0x00000003 // 4-bit data 60 #define SSI_CR0_DSS_5 0x00000004 // 5-bit data 61 #define SSI_CR0_DSS_6 0x00000005 // 6-bit data 62 #define SSI_CR0_DSS_7 0x00000006 // 7-bit data 63 #define SSI_CR0_DSS_8 0x00000007 // 8-bit data 64 #define SSI_CR0_DSS_9 0x00000008 // 9-bit data 65 #define SSI_CR0_DSS_10 0x00000009 // 10-bit data 66 #define SSI_CR0_DSS_11 0x0000000A // 11-bit data 67 #define SSI_CR0_DSS_12 0x0000000B // 12-bit data 68 #define SSI_CR0_DSS_13 0x0000000C // 13-bit data 69 #define SSI_CR0_DSS_14 0x0000000D // 14-bit data 70 #define SSI_CR0_DSS_15 0x0000000E // 15-bit data 71 #define SSI_CR0_DSS_16 0x0000000F // 16-bit data 72 #define SSI_CR0_SCR_S 8 73 74 //***************************************************************************** 75 // 76 // The following are defines for the bit fields in the SSI_O_CR1 register. 77 // 78 //***************************************************************************** 79 #define SSI_CR1_EOT 0x00000010 // End of Transmission 80 #define SSI_CR1_SOD 0x00000008 // SSI Slave Mode Output Disable 81 #define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select 82 #define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port 83 // Enable 84 #define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode 85 86 //***************************************************************************** 87 // 88 // The following are defines for the bit fields in the SSI_O_DR register. 89 // 90 //***************************************************************************** 91 #define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data 92 #define SSI_DR_DATA_S 0 93 94 //***************************************************************************** 95 // 96 // The following are defines for the bit fields in the SSI_O_SR register. 97 // 98 //***************************************************************************** 99 #define SSI_SR_BSY 0x00000010 // SSI Busy Bit 100 #define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full 101 #define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty 102 #define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full 103 #define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty 104 105 //***************************************************************************** 106 // 107 // The following are defines for the bit fields in the SSI_O_CPSR register. 108 // 109 //***************************************************************************** 110 #define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor 111 #define SSI_CPSR_CPSDVSR_S 0 112 113 //***************************************************************************** 114 // 115 // The following are defines for the bit fields in the SSI_O_IM register. 116 // 117 //***************************************************************************** 118 #define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask 119 #define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask 120 #define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt 121 // Mask 122 #define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt 123 // Mask 124 125 //***************************************************************************** 126 // 127 // The following are defines for the bit fields in the SSI_O_RIS register. 128 // 129 //***************************************************************************** 130 #define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt 131 // Status 132 #define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt 133 // Status 134 #define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw 135 // Interrupt Status 136 #define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw 137 // Interrupt Status 138 139 //***************************************************************************** 140 // 141 // The following are defines for the bit fields in the SSI_O_MIS register. 142 // 143 //***************************************************************************** 144 #define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked 145 // Interrupt Status 146 #define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked 147 // Interrupt Status 148 #define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked 149 // Interrupt Status 150 #define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked 151 // Interrupt Status 152 153 //***************************************************************************** 154 // 155 // The following are defines for the bit fields in the SSI_O_ICR register. 156 // 157 //***************************************************************************** 158 #define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt 159 // Clear 160 #define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt 161 // Clear 162 163 //***************************************************************************** 164 // 165 // The following are defines for the bit fields in the SSI_O_DMACTL register. 166 // 167 //***************************************************************************** 168 #define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable 169 #define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable 170 171 //***************************************************************************** 172 // 173 // The following are defines for the bit fields in the SSI_O_CC register. 174 // 175 //***************************************************************************** 176 #define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source 177 #define SSI_CC_CS_SYSPLL 0x00000000 // Either the system clock (if the 178 // PLL bypass is in effect) or the 179 // PLL output (default) 180 #define SSI_CC_CS_PIOSC 0x00000001 // PIOSC 181 182 //***************************************************************************** 183 // 184 // The following definitions are deprecated. 185 // 186 //***************************************************************************** 187 #ifndef DEPRECATED 188 189 //***************************************************************************** 190 // 191 // The following are deprecated defines for the bit fields in the SSI_O_CR0 192 // register. 193 // 194 //***************************************************************************** 195 #define SSI_CR0_SCR 0x0000FF00 // Serial clock rate 196 #define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask 197 #define SSI_CR0_DSS 0x0000000F // Data size select 198 199 //***************************************************************************** 200 // 201 // The following are deprecated defines for the bit fields in the SSI_O_CPSR 202 // register. 203 // 204 //***************************************************************************** 205 #define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale 206 207 //***************************************************************************** 208 // 209 // The following are deprecated defines for the SSI controller's FIFO size. 210 // 211 //***************************************************************************** 212 #define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO 213 #define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO 214 215 //***************************************************************************** 216 // 217 // The following are deprecated defines for the bit fields in the interrupt 218 // mask set and clear, raw interrupt, masked interrupt, and interrupt clear 219 // registers. 220 // 221 //***************************************************************************** 222 #define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt 223 #define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt 224 #define SSI_INT_RXTO 0x00000002 // RX timeout interrupt 225 #define SSI_INT_RXOR 0x00000001 // RX overrun interrupt 226 227 #endif 228 229 #endif // __HW_SSI_H__ 230