1 //***************************************************************************** 2 // 3 // hw_timer.h - Defines and macros used when accessing the timer. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_TIMER_H__ 26 #define __HW_TIMER_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the Timer register offsets. 31 // 32 //***************************************************************************** 33 #define TIMER_O_CFG 0x00000000 // GPTM Configuration 34 #define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode 35 #define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode 36 #define TIMER_O_CTL 0x0000000C // GPTM Control 37 #define TIMER_O_SYNC 0x00000010 // GPTM Synchronize 38 #define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask 39 #define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status 40 #define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status 41 #define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear 42 #define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load 43 #define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load 44 #define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match 45 #define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match 46 #define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale 47 #define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale 48 #define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match 49 #define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match 50 #define TIMER_O_TAR 0x00000048 // GPTM Timer A 51 #define TIMER_O_TBR 0x0000004C // GPTM Timer B 52 #define TIMER_O_TAV 0x00000050 // GPTM Timer A Value 53 #define TIMER_O_TBV 0x00000054 // GPTM Timer B Value 54 #define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide 55 #define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot 56 #define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot 57 #define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value 58 #define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value 59 #define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties 60 61 //***************************************************************************** 62 // 63 // The following are defines for the bit fields in the TIMER_O_CFG register. 64 // 65 //***************************************************************************** 66 #define TIMER_CFG_M 0x00000007 // GPTM Configuration 67 #define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32-bit timer configuration 68 #define TIMER_CFG_32_BIT_RTC 0x00000001 // 32-bit real-time clock (RTC) 69 // counter configuration 70 #define TIMER_CFG_16_BIT 0x00000004 // 16-bit timer configuration. The 71 // function is controlled by bits 72 // 1:0 of GPTMTAMR and GPTMTBMR 73 74 //***************************************************************************** 75 // 76 // The following are defines for the bit fields in the TIMER_O_TAMR register. 77 // 78 //***************************************************************************** 79 #define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy 80 // Operation 81 #define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register 82 // Update 83 #define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt 84 // Enable 85 #define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write 86 #define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode 87 #define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger 88 #define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt 89 // Enable 90 #define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction 91 #define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode 92 // Select 93 #define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode 94 #define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode 95 #define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode 96 #define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode 97 #define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode 98 99 //***************************************************************************** 100 // 101 // The following are defines for the bit fields in the TIMER_O_TBMR register. 102 // 103 //***************************************************************************** 104 #define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy 105 // Operation 106 #define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register 107 // Update 108 #define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt 109 // Enable 110 #define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write 111 #define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode 112 #define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger 113 #define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt 114 // Enable 115 #define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction 116 #define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode 117 // Select 118 #define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode 119 #define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode 120 #define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode 121 #define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode 122 #define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode 123 124 //***************************************************************************** 125 // 126 // The following are defines for the bit fields in the TIMER_O_CTL register. 127 // 128 //***************************************************************************** 129 #define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level 130 #define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger 131 // Enable 132 #define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode 133 #define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge 134 #define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge 135 #define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges 136 #define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable 137 #define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable 138 #define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level 139 #define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger 140 // Enable 141 #define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Enable 142 #define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode 143 #define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge 144 #define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge 145 #define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges 146 #define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable 147 #define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable 148 149 //***************************************************************************** 150 // 151 // The following are defines for the bit fields in the TIMER_O_SYNC register. 152 // 153 //***************************************************************************** 154 #define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer 155 // 5 156 #define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not 157 // affected 158 #define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of 159 // GPTM 32/64-Bit Timer 5 is 160 // triggered 161 #define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of 162 // GPTM 32/64-Bit Timer 5 is 163 // triggered 164 #define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A 165 // and Timer B of GPTM 32/64-Bit 166 // Timer 5 is triggered 167 #define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer 168 // 4 169 #define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not 170 // affected 171 #define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of 172 // GPTM 32/64-Bit Timer 4 is 173 // triggered 174 #define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of 175 // GPTM 32/64-Bit Timer 4 is 176 // triggered 177 #define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A 178 // and Timer B of GPTM 32/64-Bit 179 // Timer 4 is triggered 180 #define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer 181 // 3 182 #define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not 183 // affected 184 #define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of 185 // GPTM 32/64-Bit Timer 3 is 186 // triggered 187 #define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of 188 // GPTM 32/64-Bit Timer 3 is 189 // triggered 190 #define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A 191 // and Timer B of GPTM 32/64-Bit 192 // Timer 3 is triggered 193 #define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer 194 // 2 195 #define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not 196 // affected 197 #define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of 198 // GPTM 32/64-Bit Timer 2 is 199 // triggered 200 #define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of 201 // GPTM 32/64-Bit Timer 2 is 202 // triggered 203 #define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A 204 // and Timer B of GPTM 32/64-Bit 205 // Timer 2 is triggered 206 #define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer 207 // 1 208 #define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not 209 // affected 210 #define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of 211 // GPTM 32/64-Bit Timer 1 is 212 // triggered 213 #define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of 214 // GPTM 32/64-Bit Timer 1 is 215 // triggered 216 #define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A 217 // and Timer B of GPTM 32/64-Bit 218 // Timer 1 is triggered 219 #define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer 220 // 0 221 #define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not 222 // affected 223 #define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of 224 // GPTM 32/64-Bit Timer 0 is 225 // triggered 226 #define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of 227 // GPTM 32/64-Bit Timer 0 is 228 // triggered 229 #define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A 230 // and Timer B of GPTM 32/64-Bit 231 // Timer 0 is triggered 232 #define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM 16/32-Bit Timer 233 // 5 234 #define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM 16/32-Bit Timer 5 is not 235 // affected 236 #define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of 237 // GPTM 16/32-Bit Timer 5 is 238 // triggered 239 #define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of 240 // GPTM 16/32-Bit Timer 5 is 241 // triggered 242 #define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A 243 // and Timer B of GPTM 16/32-Bit 244 // Timer 5 is triggered 245 #define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM 16/32-Bit Timer 246 // 4 247 #define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM 16/32-Bit Timer 4 is not 248 // affected 249 #define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of 250 // GPTM 16/32-Bit Timer 4 is 251 // triggered 252 #define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of 253 // GPTM 16/32-Bit Timer 4 is 254 // triggered 255 #define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A 256 // and Timer B of GPTM 16/32-Bit 257 // Timer 4 is triggered 258 #define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM 16/32-Bit Timer 259 // 3 260 #define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM 16/32-Bit Timer 3 is not 261 // affected 262 #define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of 263 // GPTM 16/32-Bit Timer 3 is 264 // triggered 265 #define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of 266 // GPTM 16/32-Bit Timer 3 is 267 // triggered 268 #define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A 269 // and Timer B of GPTM 16/32-Bit 270 // Timer 3 is triggered 271 #define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM 16/32-Bit Timer 272 // 2 273 #define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM 16/32-Bit Timer 2 is not 274 // affected 275 #define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of 276 // GPTM 16/32-Bit Timer 2 is 277 // triggered 278 #define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of 279 // GPTM 16/32-Bit Timer 2 is 280 // triggered 281 #define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A 282 // and Timer B of GPTM 16/32-Bit 283 // Timer 2 is triggered 284 #define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM 16/32-Bit Timer 285 // 1 286 #define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM 16/32-Bit Timer 1 is not 287 // affected 288 #define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of 289 // GPTM 16/32-Bit Timer 1 is 290 // triggered 291 #define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of 292 // GPTM 16/32-Bit Timer 1 is 293 // triggered 294 #define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A 295 // and Timer B of GPTM 16/32-Bit 296 // Timer 1 is triggered 297 #define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM 16/32-Bit Timer 298 // 0 299 #define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM 16/32-Bit Timer 0 is not 300 // affected 301 #define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of 302 // GPTM 16/32-Bit Timer 0 is 303 // triggered 304 #define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of 305 // GPTM 16/32-Bit Timer 0 is 306 // triggered 307 #define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A 308 // and Timer B of GPTM 16/32-Bit 309 // Timer 0 is triggered 310 311 //***************************************************************************** 312 // 313 // The following are defines for the bit fields in the TIMER_O_IMR register. 314 // 315 //***************************************************************************** 316 #define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit GPTM Write Update 317 // Error Interrupt Mask 318 #define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Mode Match 319 // Interrupt Mask 320 #define TIMER_IMR_CBEIM 0x00000400 // GPTM Capture B Event Interrupt 321 // Mask 322 #define TIMER_IMR_CBMIM 0x00000200 // GPTM Capture B Match Interrupt 323 // Mask 324 #define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt 325 // Mask 326 #define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Mode Match 327 // Interrupt Mask 328 #define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask 329 #define TIMER_IMR_CAEIM 0x00000004 // GPTM Capture A Event Interrupt 330 // Mask 331 #define TIMER_IMR_CAMIM 0x00000002 // GPTM Capture A Match Interrupt 332 // Mask 333 #define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt 334 // Mask 335 336 //***************************************************************************** 337 // 338 // The following are defines for the bit fields in the TIMER_O_RIS register. 339 // 340 //***************************************************************************** 341 #define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit GPTM Write Update 342 // Error Raw Interrupt Status 343 #define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Mode Match Raw 344 // Interrupt 345 #define TIMER_RIS_CBERIS 0x00000400 // GPTM Capture B Event Raw 346 // Interrupt 347 #define TIMER_RIS_CBMRIS 0x00000200 // GPTM Capture B Match Raw 348 // Interrupt 349 #define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw 350 // Interrupt 351 #define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Mode Match Raw 352 // Interrupt 353 #define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt 354 #define TIMER_RIS_CAERIS 0x00000004 // GPTM Capture A Event Raw 355 // Interrupt 356 #define TIMER_RIS_CAMRIS 0x00000002 // GPTM Capture A Match Raw 357 // Interrupt 358 #define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw 359 // Interrupt 360 361 //***************************************************************************** 362 // 363 // The following are defines for the bit fields in the TIMER_O_MIS register. 364 // 365 //***************************************************************************** 366 #define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit GPTM Write Update 367 // Error Masked Interrupt Status 368 #define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Mode Match Masked 369 // Interrupt 370 #define TIMER_MIS_CBEMIS 0x00000400 // GPTM Capture B Event Masked 371 // Interrupt 372 #define TIMER_MIS_CBMMIS 0x00000200 // GPTM Capture B Match Masked 373 // Interrupt 374 #define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked 375 // Interrupt 376 #define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Mode Match Masked 377 // Interrupt 378 #define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt 379 #define TIMER_MIS_CAEMIS 0x00000004 // GPTM Capture A Event Masked 380 // Interrupt 381 #define TIMER_MIS_CAMMIS 0x00000002 // GPTM Capture A Match Masked 382 // Interrupt 383 #define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked 384 // Interrupt 385 386 //***************************************************************************** 387 // 388 // The following are defines for the bit fields in the TIMER_O_ICR register. 389 // 390 //***************************************************************************** 391 #define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit GPTM Write Update 392 // Error Interrupt Clear 393 #define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Mode Match 394 // Interrupt Clear 395 #define TIMER_ICR_CBECINT 0x00000400 // GPTM Capture B Event Interrupt 396 // Clear 397 #define TIMER_ICR_CBMCINT 0x00000200 // GPTM Capture B Match Interrupt 398 // Clear 399 #define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt 400 // Clear 401 #define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Mode Match 402 // Interrupt Clear 403 #define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear 404 #define TIMER_ICR_CAECINT 0x00000004 // GPTM Capture A Event Interrupt 405 // Clear 406 #define TIMER_ICR_CAMCINT 0x00000002 // GPTM Capture A Match Interrupt 407 // Clear 408 #define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw 409 // Interrupt 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the TIMER_O_TAILR register. 414 // 415 //***************************************************************************** 416 #define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load 417 // Register 418 #define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM Timer A Interval Load 419 // Register High 420 #define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM Timer A Interval Load 421 // Register Low 422 #define TIMER_TAILR_TAILRH_S 16 423 #define TIMER_TAILR_TAILRL_S 0 424 #define TIMER_TAILR_S 0 425 426 //***************************************************************************** 427 // 428 // The following are defines for the bit fields in the TIMER_O_TBILR register. 429 // 430 //***************************************************************************** 431 #define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load 432 // Register 433 #define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM Timer B Interval Load 434 // Register 435 #define TIMER_TBILR_TBILRL_S 0 436 #define TIMER_TBILR_S 0 437 438 //***************************************************************************** 439 // 440 // The following are defines for the bit fields in the TIMER_O_TAMATCHR 441 // register. 442 // 443 //***************************************************************************** 444 #define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register 445 #define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM Timer A Match Register High 446 #define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM Timer A Match Register Low 447 #define TIMER_TAMATCHR_TAMRH_S 16 448 #define TIMER_TAMATCHR_TAMRL_S 0 449 #define TIMER_TAMATCHR_TAMR_S 0 450 451 //***************************************************************************** 452 // 453 // The following are defines for the bit fields in the TIMER_O_TBMATCHR 454 // register. 455 // 456 //***************************************************************************** 457 #define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register 458 #define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM Timer B Match Register Low 459 #define TIMER_TBMATCHR_TBMR_S 0 460 #define TIMER_TBMATCHR_TBMRL_S 0 461 462 //***************************************************************************** 463 // 464 // The following are defines for the bit fields in the TIMER_O_TAPR register. 465 // 466 //***************************************************************************** 467 #define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte 468 #define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale 469 #define TIMER_TAPR_TAPSRH_S 8 470 #define TIMER_TAPR_TAPSR_S 0 471 472 //***************************************************************************** 473 // 474 // The following are defines for the bit fields in the TIMER_O_TBPR register. 475 // 476 //***************************************************************************** 477 #define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte 478 #define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale 479 #define TIMER_TBPR_TBPSRH_S 8 480 #define TIMER_TBPR_TBPSR_S 0 481 482 //***************************************************************************** 483 // 484 // The following are defines for the bit fields in the TIMER_O_TAPMR register. 485 // 486 //***************************************************************************** 487 #define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High 488 // Byte 489 #define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match 490 #define TIMER_TAPMR_TAPSMRH_S 8 491 #define TIMER_TAPMR_TAPSMR_S 0 492 493 //***************************************************************************** 494 // 495 // The following are defines for the bit fields in the TIMER_O_TBPMR register. 496 // 497 //***************************************************************************** 498 #define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High 499 // Byte 500 #define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match 501 #define TIMER_TBPMR_TBPSMRH_S 8 502 #define TIMER_TBPMR_TBPSMR_S 0 503 504 //***************************************************************************** 505 // 506 // The following are defines for the bit fields in the TIMER_O_TAR register. 507 // 508 //***************************************************************************** 509 #define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register 510 #define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM Timer A Register High 511 #define TIMER_TAR_TARL_M 0x0000FFFF // GPTM Timer A Register Low 512 #define TIMER_TAR_TARH_S 16 513 #define TIMER_TAR_TARL_S 0 514 #define TIMER_TAR_S 0 515 516 //***************************************************************************** 517 // 518 // The following are defines for the bit fields in the TIMER_O_TBR register. 519 // 520 //***************************************************************************** 521 #define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register 522 #define TIMER_TBR_TBRL_M 0x00FFFFFF // GPTM Timer B 523 #define TIMER_TBR_TBRL_S 0 524 #define TIMER_TBR_S 0 525 526 //***************************************************************************** 527 // 528 // The following are defines for the bit fields in the TIMER_O_TAV register. 529 // 530 //***************************************************************************** 531 #define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value 532 #define TIMER_TAV_TAVH_M 0xFFFF0000 // GPTM Timer A Value High 533 #define TIMER_TAV_TAVL_M 0x0000FFFF // GPTM Timer A Register Low 534 #define TIMER_TAV_TAVH_S 16 535 #define TIMER_TAV_TAVL_S 0 536 #define TIMER_TAV_S 0 537 538 //***************************************************************************** 539 // 540 // The following are defines for the bit fields in the TIMER_O_TBV register. 541 // 542 //***************************************************************************** 543 #define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value 544 #define TIMER_TBV_TBVL_M 0x0000FFFF // GPTM Timer B Register 545 #define TIMER_TBV_TBVL_S 0 546 #define TIMER_TBV_S 0 547 548 //***************************************************************************** 549 // 550 // The following are defines for the bit fields in the TIMER_O_RTCPD register. 551 // 552 //***************************************************************************** 553 #define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value 554 #define TIMER_RTCPD_RTCPD_S 0 555 556 //***************************************************************************** 557 // 558 // The following are defines for the bit fields in the TIMER_O_TAPS register. 559 // 560 //***************************************************************************** 561 #define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot 562 #define TIMER_TAPS_PSS_S 0 563 564 //***************************************************************************** 565 // 566 // The following are defines for the bit fields in the TIMER_O_TBPS register. 567 // 568 //***************************************************************************** 569 #define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value 570 #define TIMER_TBPS_PSS_S 0 571 572 //***************************************************************************** 573 // 574 // The following are defines for the bit fields in the TIMER_O_TAPV register. 575 // 576 //***************************************************************************** 577 #define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value 578 #define TIMER_TAPV_PSV_S 0 579 580 //***************************************************************************** 581 // 582 // The following are defines for the bit fields in the TIMER_O_TBPV register. 583 // 584 //***************************************************************************** 585 #define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value 586 #define TIMER_TBPV_PSV_S 0 587 588 //***************************************************************************** 589 // 590 // The following are defines for the bit fields in the TIMER_O_PP register. 591 // 592 //***************************************************************************** 593 #define TIMER_PP_SIZE_M 0x0000000F // Count Size 594 #define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are 595 // 16 bits each with an 8-bit 596 // prescale counter 597 #define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are 598 // 32 bits each with a 16-bit 599 // prescale counter 600 601 //***************************************************************************** 602 // 603 // The following definitions are deprecated. 604 // 605 //***************************************************************************** 606 #ifndef DEPRECATED 607 608 //***************************************************************************** 609 // 610 // The following are deprecated defines for the bit fields in the TIMER_O_CFG 611 // register. 612 // 613 //***************************************************************************** 614 #define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask 615 616 //***************************************************************************** 617 // 618 // The following are deprecated defines for the bit fields in the TIMER_O_CTL 619 // register. 620 // 621 //***************************************************************************** 622 #define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask 623 #define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask 624 625 //***************************************************************************** 626 // 627 // The following are deprecated defines for the bit fields in the TIMER_O_RIS 628 // register. 629 // 630 //***************************************************************************** 631 #define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status 632 #define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status 633 #define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat 634 #define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status 635 #define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status 636 #define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status 637 #define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat 638 639 //***************************************************************************** 640 // 641 // The following are deprecated defines for the bit fields in the TIMER_O_TAILR 642 // register. 643 // 644 //***************************************************************************** 645 #define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode 646 #define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value 647 648 //***************************************************************************** 649 // 650 // The following are deprecated defines for the bit fields in the TIMER_O_TBILR 651 // register. 652 // 653 //***************************************************************************** 654 #define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value 655 656 //***************************************************************************** 657 // 658 // The following are deprecated defines for the bit fields in the 659 // TIMER_O_TAMATCHR register. 660 // 661 //***************************************************************************** 662 #define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode 663 #define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value 664 665 //***************************************************************************** 666 // 667 // The following are deprecated defines for the bit fields in the 668 // TIMER_O_TBMATCHR register. 669 // 670 //***************************************************************************** 671 #define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value 672 673 //***************************************************************************** 674 // 675 // The following are deprecated defines for the bit fields in the TIMER_O_TAR 676 // register. 677 // 678 //***************************************************************************** 679 #define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode 680 #define TIMER_TAR_TARL 0x0000FFFF // TimerA value 681 682 //***************************************************************************** 683 // 684 // The following are deprecated defines for the bit fields in the TIMER_O_TBR 685 // register. 686 // 687 //***************************************************************************** 688 #define TIMER_TBR_TBRL 0x0000FFFF // TimerB value 689 690 //***************************************************************************** 691 // 692 // The following are deprecated defines for the reset values of the timer 693 // registers. 694 // 695 //***************************************************************************** 696 #define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV 697 #define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV 698 #define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV 699 #define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV 700 #define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV 701 #define TIMER_RV_TBR 0x0000FFFF // TimerB register RV 702 #define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV 703 #define TIMER_RV_CFG 0x00000000 // Configuration register RV 704 #define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV 705 #define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV 706 #define TIMER_RV_CTL 0x00000000 // Control register RV 707 #define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV 708 #define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV 709 #define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV 710 #define TIMER_RV_RIS 0x00000000 // Interrupt status register RV 711 #define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV 712 #define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV 713 #define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV 714 715 //***************************************************************************** 716 // 717 // The following are deprecated defines for the bit fields in the TIMER_TnMR 718 // register. 719 // 720 //***************************************************************************** 721 #define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select 722 #define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time 723 #define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask 724 #define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot 725 #define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic 726 #define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture 727 728 //***************************************************************************** 729 // 730 // The following are deprecated defines for the bit fields in the TIMER_TnPR 731 // register. 732 // 733 //***************************************************************************** 734 #define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value 735 736 //***************************************************************************** 737 // 738 // The following are deprecated defines for the bit fields in the TIMER_TnPMR 739 // register. 740 // 741 //***************************************************************************** 742 #define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value 743 744 #endif 745 746 #endif // __HW_TIMER_H__ 747