1 //***************************************************************************** 2 // 3 // hw_uart.h - Macros and defines used when accessing the UART hardware. 4 // 5 // Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_UART_H__ 26 #define __HW_UART_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the UART register offsets. 31 // 32 //***************************************************************************** 33 #define UART_O_DR 0x00000000 // UART Data 34 #define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear 35 #define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear 36 #define UART_O_FR 0x00000018 // UART Flag 37 #define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register 38 #define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor 39 #define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate 40 // Divisor 41 #define UART_O_LCRH 0x0000002C // UART Line Control 42 #define UART_O_CTL 0x00000030 // UART Control 43 #define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select 44 #define UART_O_IM 0x00000038 // UART Interrupt Mask 45 #define UART_O_RIS 0x0000003C // UART Raw Interrupt Status 46 #define UART_O_MIS 0x00000040 // UART Masked Interrupt Status 47 #define UART_O_ICR 0x00000044 // UART Interrupt Clear 48 #define UART_O_DMACTL 0x00000048 // UART DMA Control 49 #define UART_O_LCTL 0x00000090 // UART LIN Control 50 #define UART_O_LSS 0x00000094 // UART LIN Snap Shot 51 #define UART_O_LTIM 0x00000098 // UART LIN Timer 52 #define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address 53 #define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask 54 #define UART_O_PP 0x00000FC0 // UART Peripheral Properties 55 #define UART_O_CC 0x00000FC8 // UART Clock Configuration 56 57 //***************************************************************************** 58 // 59 // The following are defines for the bit fields in the UART_O_DR register. 60 // 61 //***************************************************************************** 62 #define UART_DR_OE 0x00000800 // UART Overrun Error 63 #define UART_DR_BE 0x00000400 // UART Break Error 64 #define UART_DR_PE 0x00000200 // UART Parity Error 65 #define UART_DR_FE 0x00000100 // UART Framing Error 66 #define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received 67 #define UART_DR_DATA_S 0 68 69 //***************************************************************************** 70 // 71 // The following are defines for the bit fields in the UART_O_RSR register. 72 // 73 //***************************************************************************** 74 #define UART_RSR_OE 0x00000008 // UART Overrun Error 75 #define UART_RSR_BE 0x00000004 // UART Break Error 76 #define UART_RSR_PE 0x00000002 // UART Parity Error 77 #define UART_RSR_FE 0x00000001 // UART Framing Error 78 79 //***************************************************************************** 80 // 81 // The following are defines for the bit fields in the UART_O_ECR register. 82 // 83 //***************************************************************************** 84 #define UART_ECR_DATA_M 0x000000FF // Error Clear 85 #define UART_ECR_DATA_S 0 86 87 //***************************************************************************** 88 // 89 // The following are defines for the bit fields in the UART_O_FR register. 90 // 91 //***************************************************************************** 92 #define UART_FR_RI 0x00000100 // Ring Indicator 93 #define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty 94 #define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full 95 #define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full 96 #define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty 97 #define UART_FR_BUSY 0x00000008 // UART Busy 98 #define UART_FR_DCD 0x00000004 // Data Carrier Detect 99 #define UART_FR_DSR 0x00000002 // Data Set Ready 100 #define UART_FR_CTS 0x00000001 // Clear To Send 101 102 //***************************************************************************** 103 // 104 // The following are defines for the bit fields in the UART_O_ILPR register. 105 // 106 //***************************************************************************** 107 #define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor 108 #define UART_ILPR_ILPDVSR_S 0 109 110 //***************************************************************************** 111 // 112 // The following are defines for the bit fields in the UART_O_IBRD register. 113 // 114 //***************************************************************************** 115 #define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor 116 #define UART_IBRD_DIVINT_S 0 117 118 //***************************************************************************** 119 // 120 // The following are defines for the bit fields in the UART_O_FBRD register. 121 // 122 //***************************************************************************** 123 #define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor 124 #define UART_FBRD_DIVFRAC_S 0 125 126 //***************************************************************************** 127 // 128 // The following are defines for the bit fields in the UART_O_LCRH register. 129 // 130 //***************************************************************************** 131 #define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select 132 #define UART_LCRH_WLEN_M 0x00000060 // UART Word Length 133 #define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) 134 #define UART_LCRH_WLEN_6 0x00000020 // 6 bits 135 #define UART_LCRH_WLEN_7 0x00000040 // 7 bits 136 #define UART_LCRH_WLEN_8 0x00000060 // 8 bits 137 #define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs 138 #define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select 139 #define UART_LCRH_EPS 0x00000004 // UART Even Parity Select 140 #define UART_LCRH_PEN 0x00000002 // UART Parity Enable 141 #define UART_LCRH_BRK 0x00000001 // UART Send Break 142 143 //***************************************************************************** 144 // 145 // The following are defines for the bit fields in the UART_O_CTL register. 146 // 147 //***************************************************************************** 148 #define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send 149 #define UART_CTL_RTSEN 0x00004000 // Enable Request to Send 150 #define UART_CTL_RTS 0x00000800 // Request to Send 151 #define UART_CTL_DTR 0x00000400 // Data Terminal Ready 152 #define UART_CTL_RXE 0x00000200 // UART Receive Enable 153 #define UART_CTL_TXE 0x00000100 // UART Transmit Enable 154 #define UART_CTL_LBE 0x00000080 // UART Loop Back Enable 155 #define UART_CTL_LIN 0x00000040 // LIN Mode Enable 156 #define UART_CTL_HSE 0x00000020 // High-Speed Enable 157 #define UART_CTL_EOT 0x00000010 // End of Transmission 158 #define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support 159 #define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode 160 #define UART_CTL_SIREN 0x00000002 // UART SIR Enable 161 #define UART_CTL_UARTEN 0x00000001 // UART Enable 162 163 //***************************************************************************** 164 // 165 // The following are defines for the bit fields in the UART_O_IFLS register. 166 // 167 //***************************************************************************** 168 #define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO 169 // Level Select 170 #define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full 171 #define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full 172 #define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default) 173 #define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full 174 #define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full 175 #define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO 176 // Level Select 177 #define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full 178 #define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full 179 #define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default) 180 #define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full 181 #define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full 182 183 //***************************************************************************** 184 // 185 // The following are defines for the bit fields in the UART_O_IM register. 186 // 187 //***************************************************************************** 188 #define UART_IM_LME5IM 0x00008000 // LIN Mode Edge 5 Interrupt Mask 189 #define UART_IM_LME1IM 0x00004000 // LIN Mode Edge 1 Interrupt Mask 190 #define UART_IM_LMSBIM 0x00002000 // LIN Mode Sync Break Interrupt 191 // Mask 192 #define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask 193 #define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt 194 // Mask 195 #define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask 196 #define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask 197 #define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt 198 // Mask 199 #define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt 200 // Mask 201 #define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask 202 #define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask 203 #define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem 204 // Interrupt Mask 205 #define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem 206 // Interrupt Mask 207 #define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem 208 // Interrupt Mask 209 #define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem 210 // Interrupt Mask 211 212 //***************************************************************************** 213 // 214 // The following are defines for the bit fields in the UART_O_RIS register. 215 // 216 //***************************************************************************** 217 #define UART_RIS_LME5RIS 0x00008000 // LIN Mode Edge 5 Raw Interrupt 218 // Status 219 #define UART_RIS_LME1RIS 0x00004000 // LIN Mode Edge 1 Raw Interrupt 220 // Status 221 #define UART_RIS_LMSBRIS 0x00002000 // LIN Mode Sync Break Raw 222 // Interrupt Status 223 #define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status 224 #define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt 225 // Status 226 #define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt 227 // Status 228 #define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt 229 // Status 230 #define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt 231 // Status 232 #define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw 233 // Interrupt Status 234 #define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt 235 // Status 236 #define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt 237 // Status 238 #define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw 239 // Interrupt Status 240 #define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem 241 // Raw Interrupt Status 242 #define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw 243 // Interrupt Status 244 #define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw 245 // Interrupt Status 246 247 //***************************************************************************** 248 // 249 // The following are defines for the bit fields in the UART_O_MIS register. 250 // 251 //***************************************************************************** 252 #define UART_MIS_LME5MIS 0x00008000 // LIN Mode Edge 5 Masked Interrupt 253 // Status 254 #define UART_MIS_LME1MIS 0x00004000 // LIN Mode Edge 1 Masked Interrupt 255 // Status 256 #define UART_MIS_LMSBMIS 0x00002000 // LIN Mode Sync Break Masked 257 // Interrupt Status 258 #define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt 259 // Status 260 #define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked 261 // Interrupt Status 262 #define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked 263 // Interrupt Status 264 #define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked 265 // Interrupt Status 266 #define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked 267 // Interrupt Status 268 #define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked 269 // Interrupt Status 270 #define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt 271 // Status 272 #define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt 273 // Status 274 #define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked 275 // Interrupt Status 276 #define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem 277 // Masked Interrupt Status 278 #define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked 279 // Interrupt Status 280 #define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked 281 // Interrupt Status 282 283 //***************************************************************************** 284 // 285 // The following are defines for the bit fields in the UART_O_ICR register. 286 // 287 //***************************************************************************** 288 #define UART_ICR_LME5IC 0x00008000 // LIN Mode Edge 5 Interrupt Clear 289 #define UART_ICR_LME1IC 0x00004000 // LIN Mode Edge 1 Interrupt Clear 290 #define UART_ICR_LMSBIC 0x00002000 // LIN Mode Sync Break Interrupt 291 // Clear 292 #define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear 293 #define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear 294 #define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear 295 #define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear 296 #define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear 297 #define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear 298 #define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear 299 #define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear 300 #define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem 301 // Interrupt Clear 302 #define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem 303 // Interrupt Clear 304 #define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem 305 // Interrupt Clear 306 #define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem 307 // Interrupt Clear 308 309 //***************************************************************************** 310 // 311 // The following are defines for the bit fields in the UART_O_DMACTL register. 312 // 313 //***************************************************************************** 314 #define UART_DMACTL_DMAERR 0x00000004 // DMA on Error 315 #define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable 316 #define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable 317 318 //***************************************************************************** 319 // 320 // The following are defines for the bit fields in the UART_O_LCTL register. 321 // 322 //***************************************************************************** 323 #define UART_LCTL_BLEN_M 0x00000030 // Sync Break Length 324 #define UART_LCTL_BLEN_13T 0x00000000 // Sync break length is 13T bits 325 // (default) 326 #define UART_LCTL_BLEN_14T 0x00000010 // Sync break length is 14T bits 327 #define UART_LCTL_BLEN_15T 0x00000020 // Sync break length is 15T bits 328 #define UART_LCTL_BLEN_16T 0x00000030 // Sync break length is 16T bits 329 #define UART_LCTL_MASTER 0x00000001 // LIN Master Enable 330 331 //***************************************************************************** 332 // 333 // The following are defines for the bit fields in the UART_O_LSS register. 334 // 335 //***************************************************************************** 336 #define UART_LSS_TSS_M 0x0000FFFF // Timer Snap Shot 337 #define UART_LSS_TSS_S 0 338 339 //***************************************************************************** 340 // 341 // The following are defines for the bit fields in the UART_O_LTIM register. 342 // 343 //***************************************************************************** 344 #define UART_LTIM_TIMER_M 0x0000FFFF // Timer Value 345 #define UART_LTIM_TIMER_S 0 346 347 //***************************************************************************** 348 // 349 // The following are defines for the bit fields in the UART_O_9BITADDR 350 // register. 351 // 352 //***************************************************************************** 353 #define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode 354 #define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode 355 #define UART_9BITADDR_ADDR_S 0 356 357 //***************************************************************************** 358 // 359 // The following are defines for the bit fields in the UART_O_9BITAMASK 360 // register. 361 // 362 //***************************************************************************** 363 #define UART_9BITAMASK_RANGE_M 0x0000FF00 // Self Address Range for 9-Bit 364 // Mode 365 #define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode 366 #define UART_9BITAMASK_RANGE_S 8 367 #define UART_9BITAMASK_MASK_S 0 368 369 //***************************************************************************** 370 // 371 // The following are defines for the bit fields in the UART_O_PP register. 372 // 373 //***************************************************************************** 374 #define UART_PP_NB 0x00000002 // 9-Bit Support 375 #define UART_PP_SC 0x00000001 // Smart Card Support 376 377 //***************************************************************************** 378 // 379 // The following are defines for the bit fields in the UART_O_CC register. 380 // 381 //***************************************************************************** 382 #define UART_CC_CS_M 0x0000000F // UART Baud Clock Source 383 #define UART_CC_CS_SYSCLK 0x00000000 // The system clock (default) 384 #define UART_CC_CS_PIOSC 0x00000001 // PIOSC 385 386 //***************************************************************************** 387 // 388 // The following definitions are deprecated. 389 // 390 //***************************************************************************** 391 #ifndef DEPRECATED 392 393 //***************************************************************************** 394 // 395 // The following are deprecated defines for the UART register offsets. 396 // 397 //***************************************************************************** 398 #define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte 399 #define UART_O_PeriphID4 0x00000FD0 400 #define UART_O_PeriphID5 0x00000FD4 401 #define UART_O_PeriphID6 0x00000FD8 402 #define UART_O_PeriphID7 0x00000FDC 403 #define UART_O_PeriphID0 0x00000FE0 404 #define UART_O_PeriphID1 0x00000FE4 405 #define UART_O_PeriphID2 0x00000FE8 406 #define UART_O_PeriphID3 0x00000FEC 407 #define UART_O_PCellID0 0x00000FF0 408 #define UART_O_PCellID1 0x00000FF4 409 #define UART_O_PCellID2 0x00000FF8 410 #define UART_O_PCellID3 0x00000FFC 411 412 //***************************************************************************** 413 // 414 // The following are deprecated defines for the bit fields in the UART_O_DR 415 // register. 416 // 417 //***************************************************************************** 418 #define UART_DR_DATA_MASK 0x000000FF // UART data 419 420 //***************************************************************************** 421 // 422 // The following are deprecated defines for the bit fields in the UART_O_IBRD 423 // register. 424 // 425 //***************************************************************************** 426 #define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor 427 428 //***************************************************************************** 429 // 430 // The following are deprecated defines for the bit fields in the UART_O_FBRD 431 // register. 432 // 433 //***************************************************************************** 434 #define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor 435 436 //***************************************************************************** 437 // 438 // The following are deprecated defines for the bit fields in the UART_O_LCR_H 439 // register. 440 // 441 //***************************************************************************** 442 #define UART_LCR_H_SPS 0x00000080 // Stick Parity Select 443 #define UART_LCR_H_WLEN 0x00000060 // Word length 444 #define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data 445 #define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data 446 #define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data 447 #define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data 448 #define UART_LCR_H_FEN 0x00000010 // Enable FIFO 449 #define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select 450 #define UART_LCR_H_EPS 0x00000004 // Even Parity Select 451 #define UART_LCR_H_PEN 0x00000002 // Parity Enable 452 #define UART_LCR_H_BRK 0x00000001 // Send Break 453 454 //***************************************************************************** 455 // 456 // The following are deprecated defines for the bit fields in the UART_O_IFLS 457 // register. 458 // 459 //***************************************************************************** 460 #define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask 461 #define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask 462 463 //***************************************************************************** 464 // 465 // The following are deprecated defines for the bit fields in the UART_O_ICR 466 // register. 467 // 468 //***************************************************************************** 469 #define UART_ICR_LME5MIC 0x00008000 // LIN Mode Edge 5 Interrupt Clear 470 #define UART_ICR_LME1MIC 0x00004000 // LIN Mode Edge 1 Interrupt Clear 471 #define UART_ICR_LMSBMIC 0x00002000 // LIN Mode Sync Break Interrupt 472 // Clear 473 #define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \ 474 UART_RSR_FE) 475 476 //***************************************************************************** 477 // 478 // The following are deprecated defines for the Reset Values for UART 479 // Registers. 480 // 481 //***************************************************************************** 482 #define UART_RV_CTL 0x00000300 483 #define UART_RV_PCellID1 0x000000F0 484 #define UART_RV_PCellID3 0x000000B1 485 #define UART_RV_FR 0x00000090 486 #define UART_RV_PeriphID2 0x00000018 487 #define UART_RV_IFLS 0x00000012 488 #define UART_RV_PeriphID0 0x00000011 489 #define UART_RV_PCellID0 0x0000000D 490 #define UART_RV_PCellID2 0x00000005 491 #define UART_RV_PeriphID3 0x00000001 492 #define UART_RV_PeriphID4 0x00000000 493 #define UART_RV_LCR_H 0x00000000 494 #define UART_RV_PeriphID6 0x00000000 495 #define UART_RV_DR 0x00000000 496 #define UART_RV_RSR 0x00000000 497 #define UART_RV_ECR 0x00000000 498 #define UART_RV_PeriphID5 0x00000000 499 #define UART_RV_RIS 0x00000000 500 #define UART_RV_FBRD 0x00000000 501 #define UART_RV_IM 0x00000000 502 #define UART_RV_MIS 0x00000000 503 #define UART_RV_ICR 0x00000000 504 #define UART_RV_PeriphID1 0x00000000 505 #define UART_RV_PeriphID7 0x00000000 506 #define UART_RV_IBRD 0x00000000 507 508 #endif 509 510 #endif // __HW_UART_H__ 511