1 //***************************************************************************** 2 // 3 // hw_udma.h - Macros for use in accessing the UDMA registers. 4 // 5 // Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of revision 8264 of the Stellaris Firmware Development Package. 22 // 23 //***************************************************************************** 24 25 #ifndef __HW_UDMA_H__ 26 #define __HW_UDMA_H__ 27 28 //***************************************************************************** 29 // 30 // The following are defines for the Micro Direct Memory Access register 31 // addresses. 32 // 33 //***************************************************************************** 34 #define UDMA_STAT 0x400FF000 // DMA Status 35 #define UDMA_CFG 0x400FF004 // DMA Configuration 36 #define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer 37 #define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control 38 // Base Pointer 39 #define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request 40 // Status 41 #define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request 42 #define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set 43 #define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear 44 #define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set 45 #define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear 46 #define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set 47 #define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear 48 #define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate 49 // Set 50 #define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate 51 // Clear 52 #define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set 53 #define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear 54 #define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear 55 #define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment 56 #define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status 57 #define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0 58 #define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1 59 #define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2 60 #define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3 61 62 //***************************************************************************** 63 // 64 // The following are defines for the bit fields in the UDMA_STAT register. 65 // 66 //***************************************************************************** 67 #define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1 68 #define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status 69 #define UDMA_STAT_STATE_IDLE 0x00000000 // Idle 70 #define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data 71 #define UDMA_STAT_STATE_RD_SRCENDP \ 72 0x00000020 // Reading source end pointer 73 #define UDMA_STAT_STATE_RD_DSTENDP \ 74 0x00000030 // Reading destination end pointer 75 #define UDMA_STAT_STATE_RD_SRCDAT \ 76 0x00000040 // Reading source data 77 #define UDMA_STAT_STATE_WR_DSTDAT \ 78 0x00000050 // Writing destination data 79 #define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to 80 // clear 81 #define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data 82 #define UDMA_STAT_STATE_STALL 0x00000080 // Stalled 83 #define UDMA_STAT_STATE_DONE 0x00000090 // Done 84 #define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined 85 #define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status 86 #define UDMA_STAT_DMACHANS_S 16 87 88 //***************************************************************************** 89 // 90 // The following are defines for the bit fields in the UDMA_CFG register. 91 // 92 //***************************************************************************** 93 #define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable 94 95 //***************************************************************************** 96 // 97 // The following are defines for the bit fields in the UDMA_CTLBASE register. 98 // 99 //***************************************************************************** 100 #define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address 101 #define UDMA_CTLBASE_ADDR_S 10 102 103 //***************************************************************************** 104 // 105 // The following are defines for the bit fields in the UDMA_ALTBASE register. 106 // 107 //***************************************************************************** 108 #define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address 109 // Pointer 110 #define UDMA_ALTBASE_ADDR_S 0 111 112 //***************************************************************************** 113 // 114 // The following are defines for the bit fields in the UDMA_WAITSTAT register. 115 // 116 //***************************************************************************** 117 #define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status 118 119 //***************************************************************************** 120 // 121 // The following are defines for the bit fields in the UDMA_SWREQ register. 122 // 123 //***************************************************************************** 124 #define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request 125 126 //***************************************************************************** 127 // 128 // The following are defines for the bit fields in the UDMA_USEBURSTSET 129 // register. 130 // 131 //***************************************************************************** 132 #define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set 133 134 //***************************************************************************** 135 // 136 // The following are defines for the bit fields in the UDMA_USEBURSTCLR 137 // register. 138 // 139 //***************************************************************************** 140 #define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear 141 142 //***************************************************************************** 143 // 144 // The following are defines for the bit fields in the UDMA_REQMASKSET 145 // register. 146 // 147 //***************************************************************************** 148 #define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set 149 150 //***************************************************************************** 151 // 152 // The following are defines for the bit fields in the UDMA_REQMASKCLR 153 // register. 154 // 155 //***************************************************************************** 156 #define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear 157 158 //***************************************************************************** 159 // 160 // The following are defines for the bit fields in the UDMA_ENASET register. 161 // 162 //***************************************************************************** 163 #define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the UDMA_ENACLR register. 168 // 169 //***************************************************************************** 170 #define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear 171 172 //***************************************************************************** 173 // 174 // The following are defines for the bit fields in the UDMA_ALTSET register. 175 // 176 //***************************************************************************** 177 #define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set 178 179 //***************************************************************************** 180 // 181 // The following are defines for the bit fields in the UDMA_ALTCLR register. 182 // 183 //***************************************************************************** 184 #define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear 185 186 //***************************************************************************** 187 // 188 // The following are defines for the bit fields in the UDMA_PRIOSET register. 189 // 190 //***************************************************************************** 191 #define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set 192 193 //***************************************************************************** 194 // 195 // The following are defines for the bit fields in the UDMA_PRIOCLR register. 196 // 197 //***************************************************************************** 198 #define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear 199 200 //***************************************************************************** 201 // 202 // The following are defines for the bit fields in the UDMA_ERRCLR register. 203 // 204 //***************************************************************************** 205 #define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status 206 207 //***************************************************************************** 208 // 209 // The following are defines for the bit fields in the UDMA_CHASGN register. 210 // 211 //***************************************************************************** 212 #define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select 213 #define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel 214 // assignment 215 #define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel 216 // assignment 217 218 //***************************************************************************** 219 // 220 // The following are defines for the bit fields in the UDMA_CHIS register. 221 // 222 //***************************************************************************** 223 #define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status 224 225 //***************************************************************************** 226 // 227 // The following are defines for the bit fields in the UDMA_CHMAP0 register. 228 // 229 //***************************************************************************** 230 #define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select 231 #define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select 232 #define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select 233 #define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select 234 #define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select 235 #define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select 236 #define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select 237 #define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select 238 #define UDMA_CHMAP0_CH7SEL_S 28 239 #define UDMA_CHMAP0_CH6SEL_S 24 240 #define UDMA_CHMAP0_CH5SEL_S 20 241 #define UDMA_CHMAP0_CH4SEL_S 16 242 #define UDMA_CHMAP0_CH3SEL_S 12 243 #define UDMA_CHMAP0_CH2SEL_S 8 244 #define UDMA_CHMAP0_CH1SEL_S 4 245 #define UDMA_CHMAP0_CH0SEL_S 0 246 247 //***************************************************************************** 248 // 249 // The following are defines for the bit fields in the UDMA_CHMAP1 register. 250 // 251 //***************************************************************************** 252 #define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select 253 #define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select 254 #define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select 255 #define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select 256 #define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select 257 #define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select 258 #define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select 259 #define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select 260 #define UDMA_CHMAP1_CH15SEL_S 28 261 #define UDMA_CHMAP1_CH14SEL_S 24 262 #define UDMA_CHMAP1_CH13SEL_S 20 263 #define UDMA_CHMAP1_CH12SEL_S 16 264 #define UDMA_CHMAP1_CH11SEL_S 12 265 #define UDMA_CHMAP1_CH10SEL_S 8 266 #define UDMA_CHMAP1_CH9SEL_S 4 267 #define UDMA_CHMAP1_CH8SEL_S 0 268 269 //***************************************************************************** 270 // 271 // The following are defines for the bit fields in the UDMA_CHMAP2 register. 272 // 273 //***************************************************************************** 274 #define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select 275 #define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select 276 #define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select 277 #define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select 278 #define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select 279 #define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select 280 #define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select 281 #define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select 282 #define UDMA_CHMAP2_CH23SEL_S 28 283 #define UDMA_CHMAP2_CH22SEL_S 24 284 #define UDMA_CHMAP2_CH21SEL_S 20 285 #define UDMA_CHMAP2_CH20SEL_S 16 286 #define UDMA_CHMAP2_CH19SEL_S 12 287 #define UDMA_CHMAP2_CH18SEL_S 8 288 #define UDMA_CHMAP2_CH17SEL_S 4 289 #define UDMA_CHMAP2_CH16SEL_S 0 290 291 //***************************************************************************** 292 // 293 // The following are defines for the bit fields in the UDMA_CHMAP3 register. 294 // 295 //***************************************************************************** 296 #define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select 297 #define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select 298 #define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select 299 #define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select 300 #define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select 301 #define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select 302 #define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select 303 #define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select 304 #define UDMA_CHMAP3_CH31SEL_S 28 305 #define UDMA_CHMAP3_CH30SEL_S 24 306 #define UDMA_CHMAP3_CH29SEL_S 20 307 #define UDMA_CHMAP3_CH28SEL_S 16 308 #define UDMA_CHMAP3_CH27SEL_S 12 309 #define UDMA_CHMAP3_CH26SEL_S 8 310 #define UDMA_CHMAP3_CH25SEL_S 4 311 #define UDMA_CHMAP3_CH24SEL_S 0 312 313 //***************************************************************************** 314 // 315 // The following are defines for the Micro Direct Memory Access (uDMA) offsets. 316 // 317 //***************************************************************************** 318 #define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End 319 // Pointer 320 #define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address 321 // End Pointer 322 #define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word 323 324 //***************************************************************************** 325 // 326 // The following are defines for the bit fields in the UDMA_O_SRCENDP register. 327 // 328 //***************************************************************************** 329 #define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer 330 #define UDMA_SRCENDP_ADDR_S 0 331 332 //***************************************************************************** 333 // 334 // The following are defines for the bit fields in the UDMA_O_DSTENDP register. 335 // 336 //***************************************************************************** 337 #define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer 338 #define UDMA_DSTENDP_ADDR_S 0 339 340 //***************************************************************************** 341 // 342 // The following are defines for the bit fields in the UDMA_O_CHCTL register. 343 // 344 //***************************************************************************** 345 #define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment 346 #define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte 347 #define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word 348 #define UDMA_CHCTL_DSTINC_32 0x80000000 // Word 349 #define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment 350 #define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size 351 #define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte 352 #define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word 353 #define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word 354 #define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment 355 #define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte 356 #define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word 357 #define UDMA_CHCTL_SRCINC_32 0x08000000 // Word 358 #define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment 359 #define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size 360 #define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte 361 #define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word 362 #define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word 363 #define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size 364 #define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer 365 #define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers 366 #define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers 367 #define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers 368 #define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers 369 #define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers 370 #define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers 371 #define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers 372 #define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers 373 #define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers 374 #define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers 375 #define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1) 376 #define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst 377 #define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode 378 #define UDMA_CHCTL_XFERMODE_STOP \ 379 0x00000000 // Stop 380 #define UDMA_CHCTL_XFERMODE_BASIC \ 381 0x00000001 // Basic 382 #define UDMA_CHCTL_XFERMODE_AUTO \ 383 0x00000002 // Auto-Request 384 #define UDMA_CHCTL_XFERMODE_PINGPONG \ 385 0x00000003 // Ping-Pong 386 #define UDMA_CHCTL_XFERMODE_MEM_SG \ 387 0x00000004 // Memory Scatter-Gather 388 #define UDMA_CHCTL_XFERMODE_MEM_SGA \ 389 0x00000005 // Alternate Memory Scatter-Gather 390 #define UDMA_CHCTL_XFERMODE_PER_SG \ 391 0x00000006 // Peripheral Scatter-Gather 392 #define UDMA_CHCTL_XFERMODE_PER_SGA \ 393 0x00000007 // Alternate Peripheral 394 // Scatter-Gather 395 #define UDMA_CHCTL_XFERSIZE_S 4 396 397 //***************************************************************************** 398 // 399 // The following definitions are deprecated. 400 // 401 //***************************************************************************** 402 #ifndef DEPRECATED 403 404 //***************************************************************************** 405 // 406 // The following are deprecated defines for the Micro Direct Memory Access 407 // register addresses. 408 // 409 //***************************************************************************** 410 #define UDMA_CHALT 0x400FF500 // DMA Channel Alternate Select 411 412 //***************************************************************************** 413 // 414 // The following are deprecated defines for the bit fields in the UDMA_ENASET 415 // register. 416 // 417 //***************************************************************************** 418 #define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set 419 420 //***************************************************************************** 421 // 422 // The following are deprecated defines for the bit fields in the UDMA_CHALT 423 // register. 424 // 425 //***************************************************************************** 426 #define UDMA_CHALT_M 0xFFFFFFFF // Channel [n] Alternate Assignment 427 // Select 428 429 #endif 430 431 #endif // __HW_UDMA_H__ 432