1 //*****************************************************************************
2 //
3 // startup_gcc.c - Startup code for use with GNU tools.
4 //
5 // Copyright (c) 2011 Texas Instruments Incorporated.  All rights reserved.
6 // Software License Agreement
7 //
8 // Texas Instruments (TI) is supplying this software for use solely and
9 // exclusively on TI's microcontroller products. The software is owned by
10 // TI and/or its suppliers, and is protected under applicable copyright
11 // laws. You may not combine this software with "viral" open-source
12 // software in order to form a larger program.
13 //
14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
19 // DAMAGES, FOR ANY REASON WHATSOEVER.
20 //
21 // This is part of revision 8264 of the EK-LM4F232 Firmware Package.
22 //
23 //*****************************************************************************
24 
25 #include "inc/hw_nvic.h"
26 #include "inc/hw_types.h"
27 
28 //*****************************************************************************
29 //
30 // Forward declaration of the default fault handlers.
31 //
32 //*****************************************************************************
33 void Reset_Handler(void);
34 static void NmiSR(void);
35 static void FaultISR(void);
36 static void IntDefaultHandler(void);
37 
38 //*****************************************************************************
39 //
40 // External declaration for the interrupt handler used by the application.
41 //
42 //*****************************************************************************
43 /* RT-Thread interface */
44 static void HardFault_Handler(void);
45 static void PendSV_Handler(void);
46 static void rt_hw_timer_handler(void);
47 static void rt_hw_uart_isr_1(void);
48 //*****************************************************************************
49 //
50 // The entry point for the application.
51 //
52 //*****************************************************************************
53 extern int main(void);
54 
55 //*****************************************************************************
56 //
57 // Reserve space for the system stack.
58 //
59 //*****************************************************************************
60 static unsigned long pulStack[256];
61 
62 //*****************************************************************************
63 //
64 // The vector table.  Note that the proper constructs must be placed on this to
65 // ensure that it ends up at physical address 0x0000.0000.
66 //
67 //*****************************************************************************
68 __attribute__ ((section(".isr_vector")))
69 void (* const g_pfnVectors[])(void) =
70 {
71     (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
72                                             // The initial stack pointer
73     Reset_Handler,                          // The reset handler
74     NmiSR,                                  // The NMI handler
75     HardFault_Handler,                      // The hard fault handler
76     IntDefaultHandler,                      // The MPU fault handler
77     IntDefaultHandler,                      // The bus fault handler
78     IntDefaultHandler,                      // The usage fault handler
79     0,                                      // Reserved
80     0,                                      // Reserved
81     0,                                      // Reserved
82     0,                                      // Reserved
83     IntDefaultHandler,                      // SVCall handler
84     IntDefaultHandler,                      // Debug monitor handler
85     0,                                      // Reserved
86     PendSV_Handler,                      // The PendSV handler
87     rt_hw_timer_handler,                      // The SysTick handler
88     IntDefaultHandler,                      // GPIO Port A
89     IntDefaultHandler,                      // GPIO Port B
90     IntDefaultHandler,                      // GPIO Port C
91     IntDefaultHandler,                      // GPIO Port D
92     IntDefaultHandler,                      // GPIO Port E
93     rt_hw_uart_isr_1,                         // UART0 Rx and Tx
94     IntDefaultHandler,                      // UART1 Rx and Tx
95     IntDefaultHandler,                      // SSI0 Rx and Tx
96     IntDefaultHandler,                      // I2C0 Master and Slave
97     IntDefaultHandler,                      // PWM Fault
98     IntDefaultHandler,                      // PWM Generator 0
99     IntDefaultHandler,                      // PWM Generator 1
100     IntDefaultHandler,                      // PWM Generator 2
101     IntDefaultHandler,                      // Quadrature Encoder 0
102     IntDefaultHandler,                      // ADC Sequence 0
103     IntDefaultHandler,                      // ADC Sequence 1
104     IntDefaultHandler,                      // ADC Sequence 2
105     IntDefaultHandler,                      // ADC Sequence 3
106     IntDefaultHandler,                      // Watchdog timer
107     IntDefaultHandler,                      // Timer 0 subtimer A
108     IntDefaultHandler,                      // Timer 0 subtimer B
109     IntDefaultHandler,                      // Timer 1 subtimer A
110     IntDefaultHandler,                      // Timer 1 subtimer B
111     IntDefaultHandler,                      // Timer 2 subtimer A
112     IntDefaultHandler,                      // Timer 2 subtimer B
113     IntDefaultHandler,                      // Analog Comparator 0
114     IntDefaultHandler,                      // Analog Comparator 1
115     IntDefaultHandler,                      // Analog Comparator 2
116     IntDefaultHandler,                      // System Control (PLL, OSC, BO)
117     IntDefaultHandler,                      // FLASH Control
118     IntDefaultHandler,                      // GPIO Port F
119     IntDefaultHandler,                      // GPIO Port G
120     IntDefaultHandler,                      // GPIO Port H
121     IntDefaultHandler,                      // UART2 Rx and Tx
122     IntDefaultHandler,                      // SSI1 Rx and Tx
123     IntDefaultHandler,                      // Timer 3 subtimer A
124     IntDefaultHandler,                      // Timer 3 subtimer B
125     IntDefaultHandler,                      // I2C1 Master and Slave
126     IntDefaultHandler,                      // Quadrature Encoder 1
127     IntDefaultHandler,                      // CAN0
128     IntDefaultHandler,                      // CAN1
129     IntDefaultHandler,                      // CAN2
130     IntDefaultHandler,                      // Ethernet
131     IntDefaultHandler,                      // Hibernate
132     IntDefaultHandler,                      // USB0
133     IntDefaultHandler,                      // PWM Generator 3
134     IntDefaultHandler,                      // uDMA Software Transfer
135     IntDefaultHandler,                      // uDMA Error
136     IntDefaultHandler,                      // ADC1 Sequence 0
137     IntDefaultHandler,                      // ADC1 Sequence 1
138     IntDefaultHandler,                      // ADC1 Sequence 2
139     IntDefaultHandler,                      // ADC1 Sequence 3
140     IntDefaultHandler,                      // I2S0
141     IntDefaultHandler,                      // External Bus Interface 0
142     IntDefaultHandler,                      // GPIO Port J
143     IntDefaultHandler,                      // GPIO Port K
144     IntDefaultHandler,                      // GPIO Port L
145     IntDefaultHandler,                      // SSI2 Rx and Tx
146     IntDefaultHandler,                      // SSI3 Rx and Tx
147     IntDefaultHandler,                      // UART3 Rx and Tx
148     IntDefaultHandler,                      // UART4 Rx and Tx
149     IntDefaultHandler,                      // UART5 Rx and Tx
150     IntDefaultHandler,                      // UART6 Rx and Tx
151     IntDefaultHandler,                      // UART7 Rx and Tx
152     0,                                      // Reserved
153     0,                                      // Reserved
154     0,                                      // Reserved
155     0,                                      // Reserved
156     IntDefaultHandler,                      // I2C2 Master and Slave
157     IntDefaultHandler,                      // I2C3 Master and Slave
158     IntDefaultHandler,                      // Timer 4 subtimer A
159     IntDefaultHandler,                      // Timer 4 subtimer B
160     0,                                      // Reserved
161     0,                                      // Reserved
162     0,                                      // Reserved
163     0,                                      // Reserved
164     0,                                      // Reserved
165     0,                                      // Reserved
166     0,                                      // Reserved
167     0,                                      // Reserved
168     0,                                      // Reserved
169     0,                                      // Reserved
170     0,                                      // Reserved
171     0,                                      // Reserved
172     0,                                      // Reserved
173     0,                                      // Reserved
174     0,                                      // Reserved
175     0,                                      // Reserved
176     0,                                      // Reserved
177     0,                                      // Reserved
178     0,                                      // Reserved
179     0,                                      // Reserved
180     IntDefaultHandler,                      // Timer 5 subtimer A
181     IntDefaultHandler,                      // Timer 5 subtimer B
182     IntDefaultHandler,                      // Wide Timer 0 subtimer A
183     IntDefaultHandler,                      // Wide Timer 0 subtimer B
184     IntDefaultHandler,                      // Wide Timer 1 subtimer A
185     IntDefaultHandler,                      // Wide Timer 1 subtimer B
186     IntDefaultHandler,                      // Wide Timer 2 subtimer A
187     IntDefaultHandler,                      // Wide Timer 2 subtimer B
188     IntDefaultHandler,                      // Wide Timer 3 subtimer A
189     IntDefaultHandler,                      // Wide Timer 3 subtimer B
190     IntDefaultHandler,                      // Wide Timer 4 subtimer A
191     IntDefaultHandler,                      // Wide Timer 4 subtimer B
192     IntDefaultHandler,                      // Wide Timer 5 subtimer A
193     IntDefaultHandler,                      // Wide Timer 5 subtimer B
194     IntDefaultHandler,                      // FPU
195     IntDefaultHandler,                      // PECI 0
196     IntDefaultHandler,                      // LPC 0
197     IntDefaultHandler,                      // I2C4 Master and Slave
198     IntDefaultHandler,                      // I2C5 Master and Slave
199     IntDefaultHandler,                      // GPIO Port M
200     IntDefaultHandler,                      // GPIO Port N
201     IntDefaultHandler,                      // Quadrature Encoder 2
202     IntDefaultHandler,                      // Fan 0
203     0,                                      // Reserved
204     IntDefaultHandler,                      // GPIO Port P (Summary or P0)
205     IntDefaultHandler,                      // GPIO Port P1
206     IntDefaultHandler,                      // GPIO Port P2
207     IntDefaultHandler,                      // GPIO Port P3
208     IntDefaultHandler,                      // GPIO Port P4
209     IntDefaultHandler,                      // GPIO Port P5
210     IntDefaultHandler,                      // GPIO Port P6
211     IntDefaultHandler,                      // GPIO Port P7
212     IntDefaultHandler,                      // GPIO Port Q (Summary or Q0)
213     IntDefaultHandler,                      // GPIO Port Q1
214     IntDefaultHandler,                      // GPIO Port Q2
215     IntDefaultHandler,                      // GPIO Port Q3
216     IntDefaultHandler,                      // GPIO Port Q4
217     IntDefaultHandler,                      // GPIO Port Q5
218     IntDefaultHandler,                      // GPIO Port Q6
219     IntDefaultHandler,                      // GPIO Port Q7
220     IntDefaultHandler,                      // GPIO Port R
221     IntDefaultHandler,                      // GPIO Port S
222     IntDefaultHandler,                      // PWM 1 Generator 0
223     IntDefaultHandler,                      // PWM 1 Generator 1
224     IntDefaultHandler,                      // PWM 1 Generator 2
225     IntDefaultHandler,                      // PWM 1 Generator 3
226     IntDefaultHandler                       // PWM 1 Fault
227 };
228 
229 //*****************************************************************************
230 //
231 // The following are constructs created by the linker, indicating where the
232 // the "data" and "bss" segments reside in memory.  The initializers for the
233 // for the "data" segment resides immediately following the "text" segment.
234 //
235 //*****************************************************************************
236 extern unsigned long _sidata;
237 extern unsigned long _sdata;
238 extern unsigned long _edata;
239 extern unsigned long _sbss;
240 extern unsigned long _ebss;
241 
242 //*****************************************************************************
243 //
244 // This is the code that gets called when the processor first starts execution
245 // following a reset event.  Only the absolutely necessary set is performed,
246 // after which the application supplied entry() routine is called.  Any fancy
247 // actions (such as making decisions based on the reset cause register, and
248 // resetting the bits in that register) are left solely in the hands of the
249 // application.
250 //
251 //*****************************************************************************
252 void
Reset_Handler(void)253 Reset_Handler(void)
254 {
255     unsigned long *pulSrc, *pulDest;
256 
257     //
258     // Copy the data segment initializers from flash to SRAM.
259     //
260     pulSrc = &_sidata;
261     for(pulDest = &_sdata; pulDest < &_edata; )
262     {
263         *pulDest++ = *pulSrc++;
264     }
265 
266     //
267     // Zero fill the bss segment.
268     //
269     __asm("    ldr     r0, =_sbss\n"
270           "    ldr     r1, =_ebss\n"
271           "    mov     r2, #0\n"
272           "    .thumb_func\n"
273           "zero_loop:\n"
274           "        cmp     r0, r1\n"
275           "        it      lt\n"
276           "        strlt   r2, [r0], #4\n"
277           "        blt     zero_loop");
278 
279     //
280     // Enable the floating-point unit.  This must be done here to handle the
281     // case where main() uses floating-point and the function prologue saves
282     // floating-point registers (which will fault if floating-point is not
283     // enabled).  Any configuration of the floating-point unit using DriverLib
284     // APIs must be done here prior to the floating-point unit being enabled.
285     //
286     // Note that this does not use DriverLib since it might not be included in
287     // this project.
288     //
289     HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
290                          ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
291                         NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
292 
293     //
294     // Call the application's entry point.
295     //
296     main();
297 }
298 
299 //*****************************************************************************
300 //
301 // This is the code that gets called when the processor receives a NMI.  This
302 // simply enters an infinite loop, preserving the system state for examination
303 // by a debugger.
304 //
305 //*****************************************************************************
306 static void
NmiSR(void)307 NmiSR(void)
308 {
309     //
310     // Enter an infinite loop.
311     //
312     while(1)
313     {
314     }
315 }
316 
317 //*****************************************************************************
318 //
319 // This is the code that gets called when the processor receives a fault
320 // interrupt.  This simply enters an infinite loop, preserving the system state
321 // for examination by a debugger.
322 //
323 //*****************************************************************************
324 static void
FaultISR(void)325 FaultISR(void)
326 {
327     //
328     // Enter an infinite loop.
329     //
330     while(1)
331     {
332     }
333 }
334 
335 //*****************************************************************************
336 //
337 // This is the code that gets called when the processor receives an unexpected
338 // interrupt.  This simply enters an infinite loop, preserving the system state
339 // for examination by a debugger.
340 //
341 //*****************************************************************************
342 static void
IntDefaultHandler(void)343 IntDefaultHandler(void)
344 {
345     //
346     // Go into an infinite loop.
347     //
348     while(1)
349     {
350     }
351 }
352