1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2011-08-09 lgnq first version for LS1B DC
9 */
10
11 #include <rtthread.h>
12 #include "display_controller.h"
13
14 struct vga_struct vga_mode[] =
15 {
16 {/*"640x480_70.00"*/ 28560, 640, 664, 728, 816, 480, 481, 484, 500, },
17 {/*"640x640_60.00"*/ 33100, 640, 672, 736, 832, 640, 641, 644, 663, },
18 {/*"640x768_60.00"*/ 39690, 640, 672, 736, 832, 768, 769, 772, 795, },
19 {/*"640x800_60.00"*/ 42130, 640, 680, 744, 848, 800, 801, 804, 828, },
20 {/*"800x480_70.00"*/ 35840, 800, 832, 912, 1024, 480, 481, 484, 500, },
21 {/*"800x600_60.00"*/ 38220, 800, 832, 912, 1024, 600, 601, 604, 622, },
22 {/*"800x640_60.00"*/ 40730, 800, 832, 912, 1024, 640, 641, 644, 663, },
23 {/*"832x600_60.00"*/ 40010, 832, 864, 952, 1072, 600, 601, 604, 622, },
24 {/*"832x608_60.00"*/ 40520, 832, 864, 952, 1072, 608, 609, 612, 630, },
25 {/*"1024x480_60.00"*/ 38170, 1024, 1048, 1152, 1280, 480, 481, 484, 497, },
26 {/*"1024x600_60.00"*/ 48960, 1024, 1064, 1168, 1312, 600, 601, 604, 622, },
27 {/*"1024x640_60.00"*/ 52830, 1024, 1072, 1176, 1328, 640, 641, 644, 663, },
28 {/*"1024x768_60.00"*/ 64110, 1024, 1080, 1184, 1344, 768, 769, 772, 795, },
29 {/*"1152x764_60.00"*/ 71380, 1152, 1208, 1328, 1504, 764, 765, 768, 791, },
30 {/*"1280x800_60.00"*/ 83460, 1280, 1344, 1480, 1680, 800, 801, 804, 828, },
31 {/*"1280x1024_55.00"*/ 98600, 1280, 1352, 1488, 1696, 1024, 1025, 1028, 1057, },
32 {/*"1440x800_60.00"*/ 93800, 1440, 1512, 1664, 1888, 800, 801, 804, 828, },
33 {/*"1440x900_67.00"*/ 120280, 1440, 1528, 1680, 1920, 900, 901, 904, 935, },
34 };
35
36 rt_align(16)
37 volatile rt_uint16_t _rt_framebuffer[FB_YSIZE][FB_XSIZE];
38 static struct rt_device_graphic_info _dc_info;
39
40 #define abs(x) ((x<0)?(-x):x)
41 #define min(a,b) ((a<b)?a:b)
42
caclulate_freq(long long XIN,long long PCLK)43 int caclulate_freq(long long XIN, long long PCLK)
44 {
45 int i;
46 long long clk, clk1;
47 int start, end;
48 int mi;
49 int pll,ctrl,div,div1,frac;
50
51 pll = PLL_FREQ;
52 ctrl = PLL_DIV_PARAM;
53 rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
54 // rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
55 start = -1;
56 end = 1;
57
58 for (i=start; i<=end; i++)
59 {
60 clk = (12+i+(pll&0x3f))*33333333/2;
61 div = clk/(long)PCLK/1000;
62 clk1 = (12+i+1+(pll&0x3f))*33333333/2;
63 div1 = clk1/(long)PCLK/1000;
64 if (div!=div1)
65 break;
66 }
67
68 if (div!=div1)
69 {
70 frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
71 pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
72 ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
73 }
74 else
75 {
76 clk = (12+start+(pll&0x3f))*33333333/2;
77 clk1 = (12+end+(pll&0x3f))*33333333/2;
78 if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
79 {
80 pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
81 ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
82 }
83 else
84 {
85 pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
86 ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
87 }
88 }
89
90 rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
91 ctrl |= 0x2a00;
92 PLL_DIV_PARAM = ctrl;
93 PLL_FREQ = pll;
94 rt_thread_delay(10);
95 // initserial(0);
96 // _probe_frequencies();
97 // rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
98 return 0;
99 }
100
rt_dc_init(rt_device_t dev)101 static rt_err_t rt_dc_init(rt_device_t dev)
102 {
103 int i, out, mode=-1;
104 int val;
105
106 for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
107 {
108 if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
109 {
110 mode=i;
111 #ifdef LS1FSOC
112 // out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
113 // rt_kprintf("out=%x\n",out);
114 /*inner gpu dc logic fifo pll ctrl,must large then outclk*/
115 // *(volatile int *)0xbfd00414 = out+1;
116 /*output pix1 clock pll ctrl*/
117 // *(volatile int *)0xbfd00410 = out;
118 /*output pix2 clock pll ctrl */
119 // *(volatile int *)0xbfd00424 = out;
120 #else
121 caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
122 #endif
123 break;
124 }
125 }
126
127 if (mode<0)
128 {
129 rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
130 return;
131 }
132
133 DC_FB_CONFIG = 0x0;
134 DC_FB_CONFIG = 0x3; // // framebuffer configuration RGB565
135 DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
136 DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
137 DC_DITHER_CONFIG = 0x0;
138 DC_DITHER_TABLE_LOW = 0x0;
139 DC_DITHER_TABLE_HIGH = 0x0;
140 DC_PANEL_CONFIG = 0x80001311;
141 DC_PANEL_TIMING = 0x0;
142
143 DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
144 DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
145 DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
146 DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
147
148 #if defined(CONFIG_VIDEO_32BPP)
149 DC_FB_CONFIG = 0x00100104;
150 DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
151 #elif defined(CONFIG_VIDEO_16BPP)
152 DC_FB_CONFIG = 0x00100103;
153 DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
154 #elif defined(CONFIG_VIDEO_15BPP)
155 DC_FB_CONFIG = 0x00100102;
156 DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
157 #elif defined(CONFIG_VIDEO_12BPP)
158 DC_FB_CONFIG = 0x00100101;
159 DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
160 #else //640x480-32Bits
161 DC_FB_CONFIG = 0x00100104;
162 DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
163 #endif //32Bits
164
165 #ifdef LS1GSOC
166 /*fix ls1g dc
167 *first switch to tile mode
168 *change origin register to 0
169 *goback nomal mode
170 */
171 {
172 val = DC_FB_CONFIG;
173 DC_FB_CONFIG = val | 0x10;
174 DC_FB_BUFFER_ORIGIN = 0;
175 DC_FB_BUFFER_ORIGIN;
176 rt_thread_delay(10);
177 DC_FB_CONFIG;
178 DC_FB_CONFIG = val;
179 }
180 #endif
181
182 return RT_EOK;
183 }
184
rt_dc_control(rt_device_t dev,int cmd,void * args)185 static rt_err_t rt_dc_control(rt_device_t dev, int cmd, void *args)
186 {
187 switch (cmd)
188 {
189 case RTGRAPHIC_CTRL_RECT_UPDATE:
190 break;
191 case RTGRAPHIC_CTRL_POWERON:
192 break;
193 case RTGRAPHIC_CTRL_POWEROFF:
194 break;
195 case RTGRAPHIC_CTRL_GET_INFO:
196 rt_memcpy(args, &_dc_info, sizeof(_dc_info));
197 break;
198 case RTGRAPHIC_CTRL_SET_MODE:
199 break;
200 }
201
202 return RT_EOK;
203 }
204
rt_hw_dc_init(void)205 void rt_hw_dc_init(void)
206 {
207 rt_device_t dc = rt_malloc(sizeof(struct rt_device));
208 if (dc == RT_NULL)
209 {
210 rt_kprintf("dc == RT_NULL\n");
211 return; /* no memory yet */
212 }
213
214 _dc_info.bits_per_pixel = 16;
215 _dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
216 _dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
217 _dc_info.width = FB_XSIZE;
218 _dc_info.height = FB_YSIZE;
219
220 /* init device structure */
221 dc->type = RT_Device_Class_Graphic;
222 dc->init = rt_dc_init;
223 dc->open = RT_NULL;
224 dc->close = RT_NULL;
225 dc->control = rt_dc_control;
226 dc->user_data = (void*)&_dc_info;
227
228 /* register Display Controller device to RT-Thread */
229 rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
230 }
231