1 /*
2  * Copyright (c) 2006-2018, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2017-09-06     勤为本       first version
9  * 2021-02-02     michael5hzg@gmail.com       adapt to ls1b
10  */
11 
12 
13 #include "rtconfig.h"
14 #include "ls1b_regs.h"
15 #include "ls1b_public.h"
16 
17 
18 // 晶振的频率
19 #define AHB_CLK                 (RT_OSC_CLK)
20 #define APB_CLK                 (AHB_CLK)
21 
22 #define DIV_DC_EN			(0x1 << 31)
23 #define DIV_DC				(0x1f << 26)
24 #define DIV_CPU_EN			(0x1 << 25)
25 #define DIV_CPU				(0x1f << 20)
26 #define DIV_DDR_EN			(0x1 << 19)
27 #define DIV_DDR				(0x1f << 14)
28 
29 #define DIV_DC_SHIFT			26
30 #define DIV_CPU_SHIFT			20
31 #define DIV_DDR_SHIFT			14
32 
33 
34 /*
35  * 获取PLL频率
36  * @ret PLL频率
37  */
clk_get_pll_rate(void)38 unsigned long clk_get_pll_rate(void)
39 {
40     unsigned int ctrl;
41     unsigned long pll_rate = 0;
42 
43     ctrl = reg_read_32((volatile unsigned int *)LS1B_START_FREQ);
44 	pll_rate = (12 + (ctrl & 0x3f)) * APB_CLK / 2
45 		+ ((ctrl >> 8) & 0x3ff) * APB_CLK / 1024 / 2;
46 
47     return pll_rate;
48 }
49 
50 
51 /*
52  * 获取CPU频率
53  * @ret CPU频率
54  */
clk_get_cpu_rate(void)55 unsigned long clk_get_cpu_rate(void)
56 {
57     unsigned long pll_rate, cpu_rate;
58     unsigned int ctrl;
59 
60     pll_rate = clk_get_pll_rate();
61     ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
62 	cpu_rate = pll_rate / ((ctrl & DIV_CPU) >> DIV_CPU_SHIFT);
63 
64     return cpu_rate;
65 }
66 
67 
68 /*
69  * 获取DDR频率
70  * @ret DDR频率
71  */
clk_get_ddr_rate(void)72 unsigned long clk_get_ddr_rate(void)
73 {
74     unsigned long pll_rate, ddr_rate;
75 	unsigned int ctrl;
76 
77 	pll_rate = clk_get_pll_rate();
78 	ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
79 
80 	ddr_rate = pll_rate / ((ctrl & DIV_DDR) >> DIV_DDR_SHIFT);
81 
82     return ddr_rate;
83 }
84 
85 
86 /*
87  * 获取APB频率
88  * @ret APB频率
89  */
clk_get_apb_rate(void)90 unsigned long clk_get_apb_rate(void)
91 {
92     return clk_get_ddr_rate() / 2;
93 }
94 
95 
96 /*
97  * 获取DC频率
98  * @ret DC频率
99  */
clk_get_dc_rate(void)100 unsigned long clk_get_dc_rate(void)
101 {
102     unsigned long pll_rate, dc_rate;
103     unsigned int ctrl;
104 
105     pll_rate = clk_get_pll_rate();
106     ctrl = reg_read_32((volatile unsigned int *)LS1B_CLK_DIV_PARAM);
107 
108     dc_rate = pll_rate ;
109 
110     return dc_rate;
111 }
112 
113 
114 
115