1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2010-06-25 Bernard first version 9 * 2011-08-08 lgnq modified for Loongson LS1B 10 * 2015-07-06 chinesebear modified for Loongson LS1C 11 * 2019-12-04 Jiaxun Yang Add board config defines 12 */ 13 14 #ifndef __BOARD_H__ 15 #define __BOARD_H__ 16 #include <rtconfig.h> 17 18 #ifndef __ASSEMBLY__ 19 void rt_hw_board_init(void); 20 #endif 21 22 /* 23 * SDRAM config 24 * 25 * Take IS42S16400 SDRAM chip as a example 26 * The specfication is 27 * Size 8MB 28 * WIDTH: 16 bits 29 * COL WIDTH: 8 bits, so we should take the 8 power of 2, it's 256 30 * ROW WIDTH: 12 bits, so we take the 12 power of 2, it's 4K 31 * 32 * Please reference macro SD_PARA0 and SDRAM registers intruduction 33 * in user's manual to edit the SDRAM config. 34 */ 35 36 #if defined(RT_LS1C_BAICAIBOARD) 37 /* 8MByte IS42S16400 appeared in bacai_board V1.x V2.x */ 38 #define MEM_SIZE (0x800000) 39 #define SDRAM_WIDTH (WIDTH_16) 40 #define SDRAM_COL (COL_256) 41 #define SDRAM_ROW (ROW_4K) 42 #elif defined(RT_LS1C_OPENLOONGSON) 43 /* 32MByte appeared in SmartLoong board */ 44 #define MEM_SIZE (0x2000000) 45 #define SDRAM_WIDTH (WIDTH_16) 46 #define SDRAM_COL (COL_512) 47 #define SDRAM_ROW (ROW_8K) 48 #else 49 #error Unknown Board 50 #endif 51 52 /* Early Debug config */ 53 #define EARLY_DEBUG /* UART2 serial print debug in early stage */ 54 #define EARLY_DEBUG_BAUD (115200) 55 56 /* Clock config */ 57 #define CPU_HZ (252 * 1000000) 58 #define PLL_MULT (0x54) /* When external clock is 24Mhz PLL=504Mhz */ 59 #define SDRAM_DIV (0) /* SDRAM is CPU divided by 2*/ 60 #define CPU_DIV (2) /* CPU clock is PLL divided by 2 */ 61 62 #endif 63