1 /*
2  * Copyright (c) 2006-2022, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date                Author           Notes
8  * 2011-08-08     lgnq            first version for LS1B
9  * 2015-07-06    chinesebear   modified for loongson 1c
10   * 2018-01-06    sundm75   modified for smartloong
11 */
12 
13 #ifndef __DISPLAY_CONTROLLER_H__
14 #define __DISPLAY_CONTROLLER_H__
15 
16 #include <rtthread.h>
17 #include "ls1c.h"
18 
19 #define DC_BASE                 0xBC301240  //Display Controller
20 
21 /* Frame Buffer registers */
22 #define DC_FB_CONFIG            __REG32(DC_BASE + 0x000)
23 #define DC_FB_BUFFER_ADDR0      __REG32(DC_BASE + 0x020)
24 #define DC_FB_BUFFER_STRIDE     __REG32(DC_BASE + 0x040)
25 #define DC_FB_BUFFER_ORIGIN     __REG32(DC_BASE + 0x060)
26 #define DC_DITHER_CONFIG        __REG32(DC_BASE + 0x120)
27 #define DC_DITHER_TABLE_LOW     __REG32(DC_BASE + 0x140)
28 #define DC_DITHER_TABLE_HIGH    __REG32(DC_BASE + 0x160)
29 #define DC_PANEL_CONFIG         __REG32(DC_BASE + 0x180)
30 #define DC_PANEL_TIMING         __REG32(DC_BASE + 0x1A0)
31 #define DC_HDISPLAY             __REG32(DC_BASE + 0x1C0)
32 #define DC_HSYNC                __REG32(DC_BASE + 0x1E0)
33 #define DC_VDISPLAY             __REG32(DC_BASE + 0x240)
34 #define DC_VSYNC                __REG32(DC_BASE + 0x260)
35 #define DC_FB_BUFFER_ADDR1      __REG32(DC_BASE + 0x340)
36 
37 /* Display Controller driver for 1024x768 16bit */
38 #define FB_XSIZE        480
39 #define FB_YSIZE        272
40 #define CONFIG_VIDEO_16BPP
41 
42 #define OSC 24000000        /* Hz */
43 
44 #define K1BASE              0xA0000000
45 #define KSEG1(addr)         ((void *)(K1BASE | (rt_uint32_t)(addr)))
46 #define HW_FB_ADDR          KSEG1(_rt_framebuffer)
47 
48 struct vga_struct
49 {
50     long pclk;
51     int hr,hss,hse,hfl;
52     int vr,vss,vse,vfl;
53 };
54 
55 #endif
56