1 /*
2  * Copyright (c) 2006-2018, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018-05-08     zhuangwei    the first version
9  */
10 
11 #ifndef __DRV_UART_H__
12 #define __DRV_UART_H__
13 
14 #include "ls1c.h"
15 #include <rthw.h>
16 
17 #define DEV_CLK 252000000 // 252MHz
18 #define UART_BAUDRATE 115200
19 
20 #define UART0_BASE          0xBFE40000
21 //#define UART0_1_BASE      0xBFE41000
22 #define UART1_BASE          0xBFE44000
23 #define UART2_BASE          0xBFE48000
24 #define UART3_BASE          0xBFE4C000
25 #define UART4_BASE          0xBFE4C400
26 #define UART5_BASE          0xBFE4C500
27 #define UART6_BASE          0xBFE4C600
28 #define UART7_BASE          0xBFE4C700
29 #define UART8_BASE          0xBFE4C800
30 #define UART9_BASE          0xBFE4C900
31 #define UART10_BASE         0xBFE4Ca00
32 #define UART11_BASE         0xBFE4Cb00
33 
34 /* UART registers */
35 #define UART_DAT(base)      HWREG8(base + 0x00)
36 #define UART_IER(base)      HWREG8(base + 0x01)
37 #define UART_IIR(base)      HWREG8(base + 0x02)
38 #define UART_FCR(base)      HWREG8(base + 0x02)
39 #define UART_LCR(base)      HWREG8(base + 0x03)
40 #define UART_MCR(base)      HWREG8(base + 0x04)
41 #define UART_LSR(base)      HWREG8(base + 0x05)
42 #define UART_MSR(base)      HWREG8(base + 0x06)
43 
44 #define UART_LSB(base)      HWREG8(base + 0x00)
45 #define UART_MSB(base)      HWREG8(base + 0x01)
46 
47 /* UART0 registers */
48 #define UART0_DAT           HWREG8(UART0_BASE + 0x00)
49 #define UART0_IER           HWREG8(UART0_BASE + 0x01)
50 #define UART0_IIR           HWREG8(UART0_BASE + 0x02)
51 #define UART0_FCR           HWREG8(UART0_BASE + 0x02)
52 #define UART0_LCR           HWREG8(UART0_BASE + 0x03)
53 #define UART0_MCR           HWREG8(UART0_BASE + 0x04)
54 #define UART0_LSR           HWREG8(UART0_BASE + 0x05)
55 #define UART0_MSR           HWREG8(UART0_BASE + 0x06)
56 
57 #define UART0_LSB           HWREG8(UART0_BASE + 0x00)
58 #define UART0_MSB           HWREG8(UART0_BASE + 0x01)
59 
60 /* UART1 registers */
61 #define UART1_DAT           HWREG8(UART1_BASE + 0x00)
62 #define UART1_IER           HWREG8(UART1_BASE + 0x01)
63 #define UART1_IIR           HWREG8(UART1_BASE + 0x02)
64 #define UART1_FCR           HWREG8(UART1_BASE + 0x02)
65 #define UART1_LCR           HWREG8(UART1_BASE + 0x03)
66 #define UART1_MCR           HWREG8(UART1_BASE + 0x04)
67 #define UART1_LSR           HWREG8(UART1_BASE + 0x05)
68 #define UART1_MSR           HWREG8(UART1_BASE + 0x06)
69 
70 #define UART1_LSB           HWREG8(UART1_BASE + 0x00)
71 #define UART1_MSB           HWREG8(UART1_BASE + 0x01)
72 
73 /* UART interrupt enable register value */
74 #define UARTIER_IME     (1 << 3)
75 #define UARTIER_ILE     (1 << 2)
76 #define UARTIER_ITXE    (1 << 1)
77 #define UARTIER_IRXE    (1 << 0)
78 
79 /* UART line control register value */
80 #define UARTLCR_DLAB    (1 << 7)
81 #define UARTLCR_BCB     (1 << 6)
82 #define UARTLCR_SPB     (1 << 5)
83 #define UARTLCR_EPS     (1 << 4)
84 #define UARTLCR_PE      (1 << 3)
85 #define UARTLCR_SB      (1 << 2)
86 
87 /* UART line status register value */
88 #define UARTLSR_ERROR   (1 << 7)
89 #define UARTLSR_TE      (1 << 6)
90 #define UARTLSR_TFE     (1 << 5)
91 #define UARTLSR_BI      (1 << 4)
92 #define UARTLSR_FE      (1 << 3)
93 #define UARTLSR_PE      (1 << 2)
94 #define UARTLSR_OE      (1 << 1)
95 #define UARTLSR_DR      (1 << 0)
96 
97 void rt_hw_uart_init(void);
98 
99 
100 #endif
101