1 /*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2018-01-04 Sundm75 the first version
9 */
10
11 #include <rtthread.h>
12 #include <rtdevice.h>
13 #include "ls1c_i2c.h"
14 #include "../libraries/ls1c_pin.h"
15
16 #ifdef RT_USING_I2C
17
18 struct ls1c_i2c_bus
19 {
20 struct rt_i2c_bus_device parent;
21 rt_uint32_t u32Module;
22 };
23
rt_i2c_master_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msgs,rt_uint32_t num)24 rt_size_t rt_i2c_master_xfer(struct rt_i2c_bus_device *bus,
25 struct rt_i2c_msg *msgs,
26 rt_uint32_t num)
27 {
28 struct ls1c_i2c_bus * i2c_bus = (struct ls1c_i2c_bus *)bus;
29 ls1c_i2c_info_t i2c_info;
30 struct rt_i2c_msg *msg;
31 int i;
32 rt_int32_t ret = RT_EOK;
33 i2c_info.clock = 50000; // 50kb/s
34 i2c_info.I2Cx = i2c_bus->u32Module;
35 i2c_init(&i2c_info);
36
37 for (i = 0; i < num; i++)
38 {
39 msg = &msgs[i];
40 if (msg->flags == RT_I2C_RD)
41 {
42 i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_READ);
43 i2c_receive_ack(&i2c_info);
44 i2c_receive_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len);
45 i2c_send_stop(&i2c_info);
46 }
47 else if(msg->flags == RT_I2C_WR)
48 {
49 i2c_send_start_and_addr(&i2c_info, msg->addr, LS1C_I2C_DIRECTION_WRITE);
50 i2c_receive_ack(&i2c_info);
51 i2c_send_data(&i2c_info, (rt_uint8_t *)msg->buf, msg->len);
52 i2c_send_stop(&i2c_info);
53 }
54 ret++;
55 }
56 return ret;
57 }
58
rt_i2c_bus_control(struct rt_i2c_bus_device * bus,int cmd,void * args)59 rt_err_t rt_i2c_bus_control(struct rt_i2c_bus_device *bus,
60 int cmd,
61 void *args)
62 {
63 struct ls1c_i2c_bus * i2c_bus = (struct ls1c_i2c_bus *)bus;
64
65 RT_ASSERT(bus != RT_NULL);
66 i2c_bus = (struct ls1c_i2c_bus *)bus->parent.user_data;
67
68 RT_ASSERT(i2c_bus != RT_NULL);
69
70 switch (cmd)
71 {
72 case RT_DEVICE_CTRL_CONFIG :
73 break;
74 }
75
76 return RT_EOK;
77 }
78
79 static const struct rt_i2c_bus_device_ops ls1c_i2c_ops =
80 {
81 rt_i2c_master_xfer,
82 RT_NULL,
83 rt_i2c_bus_control
84 };
85
86
87 #ifdef RT_USING_I2C0
88 static struct ls1c_i2c_bus ls1c_i2c_bus_0 =
89 {
90 {1},
91 LS1C_I2C_0,
92 };
93 #endif
94
95 #ifdef RT_USING_I2C1
96 static struct ls1c_i2c_bus ls1c_i2c_bus_1 =
97 {
98 {1},
99 LS1C_I2C_1,
100 };
101 #endif
102
103 #ifdef RT_USING_I2C2
104 static struct ls1c_i2c_bus ls1c_i2c_bus_2 =
105 {
106 {1},
107 LS1C_I2C_2,
108 };
109 #endif
110
ls1c_hw_i2c_init(void)111 int ls1c_hw_i2c_init(void)
112 {
113 struct ls1c_i2c_bus* ls1c_i2c;
114
115 #ifdef RT_USING_I2C0
116 /*
117 pin_set_purpose(2, PIN_PURPOSE_OTHER);
118 pin_set_purpose(3, PIN_PURPOSE_OTHER);
119 pin_set_remap(2, PIN_REMAP_SECOND);
120 pin_set_remap(3, PIN_REMAP_SECOND);
121 */
122 #endif
123 #ifdef RT_USING_I2C1
124 pin_set_purpose(2, PIN_PURPOSE_OTHER);
125 pin_set_purpose(3, PIN_PURPOSE_OTHER);
126 pin_set_remap(2, PIN_REMAP_SECOND);
127 pin_set_remap(3, PIN_REMAP_SECOND);
128 #endif
129 #ifdef RT_USING_I2C2
130 pin_set_purpose(51, PIN_PURPOSE_OTHER);
131 pin_set_purpose(50, PIN_PURPOSE_OTHER);
132 pin_set_remap(51, PIN_REMAP_FOURTH);
133 pin_set_remap(50, PIN_REMAP_FOURTH);
134 #endif
135
136
137 #ifdef RT_USING_I2C0
138 ls1c_i2c = &ls1c_i2c_bus_0;
139 ls1c_i2c->parent.ops = &ls1c_i2c_ops;
140 rt_i2c_bus_device_register(&ls1c_i2c->parent, "i2c0");
141 rt_kprintf("i2c0_init!\n");
142 #endif
143 #ifdef RT_USING_I2C1
144 ls1c_i2c = &ls1c_i2c_bus_1;
145 ls1c_i2c->parent.ops = &ls1c_i2c_ops;
146 rt_i2c_bus_device_register(&ls1c_i2c->parent, "i2c1");
147 rt_kprintf("i2c1_init!\n");
148 #endif
149
150 #ifdef RT_USING_I2C2
151 ls1c_i2c = &ls1c_i2c_bus_2;
152 ls1c_i2c->parent.ops = &ls1c_i2c_ops;
153 rt_i2c_bus_device_register(&ls1c_i2c->parent, "i2c2");
154 rt_kprintf("i2c2_init!\n");
155 #endif
156
157 return RT_EOK;
158 }
159
160 INIT_BOARD_EXPORT(ls1c_hw_i2c_init);
161
162 #endif
163