1 /*
2  * Copyright (c) 2006-2022, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2019-12-04     Jiaxun Yang  Initial version
9  */
10 
11 #ifndef __RT_LS1C_SELFBOOT_H
12 #define __RT_LS1C_SELFBOOT_H
13 
14 /* SDRAM PARAM macro */
15 #define SD_FREQ (((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
16 
17 
18 /* SDRAM ROW */
19 #define ROW_1K      0x7
20 #define ROW_2K      0x0
21 #define ROW_4K      0x1
22 #define ROW_8K      0x2
23 #define ROW_16K     0x3
24 /* SDRAM COL */
25 #define COL_256     0x7
26 #define COL_512     0x0
27 #define COL_1K      0x1
28 #define COL_2K      0x2
29 #define COL_4K      0x3
30 /* SDRAM WIDTH */
31 #define WIDTH_8     0x0
32 #define WIDTH_16    0x1
33 #define WIDTH_32    0x2
34 
35 #define TRCD        3
36 #define TCL         3
37 #define TRP         3
38 #define TRFC        8
39 #define TRAS        6
40 #define TREF        0x818
41 #define TWR         2
42 
43 #define DEF_SEL     0x1
44 #define DEF_SEL_N   0x0
45 #define HANG_UP     0x1
46 #define HANG_UP_N   0x0
47 #define CFG_VALID   0x1
48 
49 #include "board.h"
50 
51 #define SD_PARA0    (0x7f<<25 | \
52                     (TRAS << 21) | \
53                     (TRFC << 17) | (TRP << 14) | (TCL << 11) | \
54                     (TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
55                     SDRAM_ROW)
56 
57 #define SD_PARA1    ((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
58 
59 #define SD_PARA1_EN ((CFG_VALID << 9) | (HANG_UP_N << 8) | \
60                     (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
61 
62 #define LS1C_CBUS_FIRST1      0xBFE011C4
63 #define LS1C_UART2_BASE       0xBFE48000
64 
65 /* UART register offset*/
66 #define LS1C_UART_DAT_OFFSET            (0)
67 #define LS1C_UART_IER_OFFSET            (1)
68 #define LS1C_UART_IIR_OFFSET            (2)
69 #define LS1C_UART_FCR_OFFSET            (2)
70 #define LS1C_UART_LCR_OFFSET            (3)
71 #define LS1C_UART_MCR_OFFSET            (4)
72 #define LS1C_UART_LSR_OFFSET            (5)
73 #define LS1C_UART_MSR_OFFSET            (6)
74 
75 #define LS1C_UART_LSB_OFFSET            (0)
76 #define LS1C_UART_MSB_OFFSET            (1)
77 
78 /* interrupt enable register */
79 #define IER_IRxE    0x1
80 #define IER_ITxE    0x2
81 #define IER_ILE     0x4
82 #define IER_IME     0x8
83 
84 /* interrupt identification register */
85 #define IIR_IMASK   0xf /* mask */
86 #define IIR_RXTOUT  0xc /* receive timeout */
87 #define IIR_RLS     0x6 /* receive line status */
88 #define IIR_RXRDY   0x4 /* receive ready */
89 #define IIR_TXRDY   0x2 /* transmit ready */
90 #define IIR_NOPEND  0x1 /* nothing */
91 #define IIR_MLSC    0x0 /* modem status */
92 #define IIR_FIFO_MASK   0xc0    /* set if FIFOs are enabled */
93 
94 /* fifo control register */
95 #define FIFO_ENABLE 0x01    /* enable fifo */
96 #define FIFO_RCV_RST    0x02    /* reset receive fifo */
97 #define FIFO_XMT_RST    0x04    /* reset transmit fifo */
98 #define FIFO_DMA_MODE   0x08    /* enable dma mode */
99 #define FIFO_TRIGGER_1  0x00    /* trigger at 1 char */
100 #define FIFO_TRIGGER_4  0x40    /* trigger at 4 chars */
101 #define FIFO_TRIGGER_8  0x80    /* trigger at 8 chars */
102 #define FIFO_TRIGGER_14 0xc0    /* trigger at 14 chars */
103 
104 /* character format control register */
105 #define CFCR_DLAB   0x80    /* divisor latch */
106 #define CFCR_SBREAK 0x40    /* send break */
107 #define CFCR_PZERO  0x30    /* zero parity */
108 #define CFCR_PONE   0x20    /* one parity */
109 #define CFCR_PEVEN  0x10    /* even parity */
110 #define CFCR_PODD   0x00    /* odd parity */
111 #define CFCR_PENAB  0x08    /* parity enable */
112 #define CFCR_STOPB  0x04    /* 2 stop bits */
113 #define CFCR_8BITS  0x03    /* 8 data bits */
114 #define CFCR_7BITS  0x02    /* 7 data bits */
115 #define CFCR_6BITS  0x01    /* 6 data bits */
116 #define CFCR_5BITS  0x00    /* 5 data bits */
117 
118 /* modem control register */
119 #define MCR_LOOPBACK    0x10    /* loopback */
120 #define MCR_IENABLE 0x08    /* output 2 = int enable */
121 #define MCR_DRS     0x04    /* output 1 = xxx */
122 #define MCR_RTS     0x02    /* enable RTS */
123 #define MCR_DTR     0x01    /* enable DTR */
124 
125 /* line status register */
126 #define LSR_RCV_FIFO    0x80    /* error in receive fifo */
127 #define LSR_TSRE    0x40    /* transmitter empty */
128 #define LSR_TXRDY   0x20    /* transmitter ready */
129 #define LSR_BI      0x10    /* break detected */
130 #define LSR_FE      0x08    /* framing error */
131 #define LSR_PE      0x04    /* parity error */
132 #define LSR_OE      0x02    /* overrun error */
133 #define LSR_RXRDY   0x01    /* receiver ready */
134 #define LSR_RCV_MASK    0x1f
135 
136 
137 /* External clock frequency */
138 #define AHB_CLK                 (24000000)
139 #define APB_CLK                 (AHB_CLK)
140 
141 
142 /* START_FREQ register bits */
143 #define M_PLL_SHIFT             (8)
144 #define M_PLL                   (0xff << M_PLL_SHIFT)
145 #define FRAC_N_SHIFT            (16)
146 #define FRAC_N                  (0xff << FRAC_N_SHIFT)
147 #define DIV_SDRAM_SHIFT         (0)
148 #define DIV_SDRAM               (0x3  << DIV_SDRAM_SHIFT)
149 
150 /* CLK_DIV_PARAM register bits */
151 #define DIV_PIX_EN              (0x1  << 31)
152 #define DIV_PIX                 (0x7f << 24)
153 #define DIV_CAM_EN              (0x1  << 23)
154 #define DIV_CAM                 (0x7f << 16)
155 #define DIV_CPU_EN              (0x1  << 15)
156 #define DIV_CPU                 (0x7f << 8)
157 #define DIV_PIX_VALID           (0x1  << 5)
158 #define DIV_PIX_SEL             (0x1  << 4)
159 #define DIV_CAM_VALID           (0x1  << 3)
160 #define DIV_CAM_SEL             (0x1  << 2)
161 #define DIV_CPU_VALID           (0x1  << 1)
162 #define DIV_CPU_SEL             (0x1  << 0)
163 
164 #define DIV_PIX_SHIFT           (24)
165 #define DIV_CAM_SHIFT           (16)
166 #define DIV_CPU_SHIFT           (8)
167 
168 #endif
169