1 /* 2 * Copyright (c) 2006-2020, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020-08-19 lizhirui porting to ls2k 9 */ 10 11 #ifndef _AHCI_H_ 12 #define _AHCI_H_ 13 14 #define AHCI_PCI_BAR 0x24 15 #define AHCI_MAX_SG 56 /* hardware max is 64K */ 16 #define AHCI_CMD_SLOT_SZ 32 17 #define AHCI_MAX_CMD_SLOT 32 18 #define AHCI_RX_FIS_SZ 256 19 #define AHCI_CMD_TBL_HDR 0x80 20 #define AHCI_CMD_TBL_CDB 0x40 21 #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) 22 #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ 23 AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) 24 #define AHCI_CMD_ATAPI (1 << 5) 25 #define AHCI_CMD_WRITE (1 << 6) 26 #define AHCI_CMD_PREFETCH (1 << 7) 27 #define AHCI_CMD_RESET (1 << 8) 28 #define AHCI_CMD_CLR_BUSY (1 << 10) 29 30 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */ 31 32 /* Global controller registers */ 33 #define HOST_CAP 0x00 /* host capabilities */ 34 #define HOST_CTL 0x04 /* global host control */ 35 #define HOST_IRQ_STAT 0x08 /* interrupt status */ 36 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ 37 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */ 38 #define HOST_CAP2 0x24 /* host capabilities, extended */ 39 40 /* HOST_CTL bits */ 41 #define HOST_RESET (1 << 0) /* reset controller; self-clear */ 42 #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */ 43 #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */ 44 45 /* Registers for each SATA port */ 46 #define PORT_LST_ADDR 0x00 /* command list DMA addr */ 47 #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */ 48 #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */ 49 #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */ 50 #define PORT_IRQ_STAT 0x10 /* interrupt status */ 51 #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */ 52 #define PORT_CMD 0x18 /* port command */ 53 #define PORT_TFDATA 0x20 /* taskfile data */ 54 #define PORT_SIG 0x24 /* device TF signature */ 55 #define PORT_CMD_ISSUE 0x38 /* command issue */ 56 #define PORT_SCR 0x28 /* SATA phy register block */ 57 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */ 58 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */ 59 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */ 60 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */ 61 62 #ifdef CONFIG_SUNXI_AHCI 63 #define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */ 64 #endif 65 66 /* PORT_IRQ_{STAT,MASK} bits */ 67 #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */ 68 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */ 69 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */ 70 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */ 71 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */ 72 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */ 73 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */ 74 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */ 75 76 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */ 77 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */ 78 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */ 79 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */ 80 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */ 81 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */ 82 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */ 83 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */ 84 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */ 85 86 #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR 87 88 #define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS 89 90 /* PORT_SCR_STAT bits */ 91 #define PORT_SCR_STAT_DET_MASK 0x3 92 #define PORT_SCR_STAT_DET_COMINIT 0x1 93 #define PORT_SCR_STAT_DET_PHYRDY 0x3 94 95 /* PORT_CMD bits */ 96 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */ 97 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */ 98 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */ 99 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */ 100 #define PORT_CMD_CLO (1 << 3) /* Command list override */ 101 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */ 102 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */ 103 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */ 104 105 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */ 106 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */ 107 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */ 108 109 #define AHCI_MAX_PORTS 32 110 111 #define ATA_FLAG_SATA (1 << 3) 112 #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */ 113 #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */ 114 #define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */ 115 #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */ 116 #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */ 117 118 struct ahci_cmd_hdr 119 { 120 u32 opts; 121 u32 status; 122 u64 tbl_addr; 123 //u32 tbl_addr_hi; 124 u32 reserved[4]; 125 }; 126 127 struct ahci_sg 128 { 129 u64 addr; 130 //u32 addr_hi; 131 u32 reserved; 132 u32 flags_size; 133 }; 134 135 struct ahci_ioports 136 { 137 void __iomem *port_mmio; 138 struct ahci_cmd_hdr *cmd_slot; 139 struct ahci_sg *cmd_tbl_sg; 140 ulong cmd_tbl; 141 u32 rx_fis; 142 }; 143 144 /** 145 * struct ahci_uc_priv - information about an AHCI controller 146 * 147 * When driver model is used, this is accessible using dev_get_uclass_priv(dev) 148 * where dev is the controller (although at present it sometimes stands alone). 149 */ 150 struct ahci_uc_priv 151 { 152 struct rt_device parent; 153 struct ahci_ioports port[AHCI_MAX_PORTS]; 154 u16 *ataid[AHCI_MAX_PORTS]; 155 u32 n_ports; 156 u32 hard_port_no; 157 u32 host_flags; 158 u32 host_set_flags; 159 void *mmio_base; 160 u32 pio_mask; 161 u32 udma_mask; 162 u32 flags; 163 u32 cap; /* cache of HOST_CAP register */ 164 u32 port_map; /* cache of HOST_PORTS_IMPL reg */ 165 u32 link_port_map; /*linkup port map*/ 166 }; 167 168 struct ahci_ops 169 { 170 /** 171 * reset() - reset the controller 172 * 173 * @dev: Controller to reset 174 * @return 0 if OK, -ve on error 175 */ 176 int (*reset)(struct rt_device *dev); 177 178 /** 179 * port_status() - get the status of a SATA port 180 * 181 * @dev: Controller to reset 182 * @port: Port number to check (0 for first) 183 * @return 0 if detected, -ENXIO if nothing on port, other -ve on error 184 */ 185 int (*port_status)(struct rt_device *dev, int port); 186 187 /** 188 * scan() - scan SATA ports 189 * 190 * @dev: Controller to scan 191 * @return 0 if OK, -ve on error 192 */ 193 int (*scan)(struct rt_device *dev); 194 }; 195 196 #define ahci_get_ops(dev) ((struct ahci_ops *)(dev)->driver->ops) 197 198 /** 199 * sata_reset() - reset the controller 200 * 201 * @dev: Controller to reset 202 * @return 0 if OK, -ve on error 203 */ 204 int sata_reset(struct rt_device *dev); 205 206 /** 207 * sata_port_status() - get the status of a SATA port 208 * 209 * @dev: Controller to reset 210 * @port: Port number to check (0 for first) 211 * @return 0 if detected, -ENXIO if nothin on port, other -ve on error 212 */ 213 int sata_dm_port_status(struct rt_device *dev, int port); 214 215 /** 216 * sata_scan() - scan SATA ports 217 * 218 * @dev: Controller to scan 219 * @return 0 if OK, -ve on error 220 */ 221 int sata_scan(struct rt_device *dev); 222 223 int ahci_init(void __iomem *base); 224 int ahci_reset(void __iomem *base); 225 226 /** 227 * ahci_init_one_dm() - set up a single AHCI port 228 * 229 * @dev: Controller to init 230 */ 231 int ahci_init_one_dm(struct rt_device *dev); 232 233 /** 234 * ahci_start_ports_dm() - start all AHCI ports for a controller 235 * 236 * @dev: Controller containing ports to start 237 */ 238 int ahci_start_ports_dm(struct rt_device *dev); 239 240 /** 241 * ahci_init_dm() - init AHCI for a controller, finding all ports 242 * 243 * @dev: Device to init 244 */ 245 int ahci_init_dm(struct rt_device *dev, void __iomem *base); 246 247 /** 248 * ahci_bind_scsi() - bind a new SCSI bus as a child 249 * 250 * Note that the SCSI bus device will itself bind block devices 251 * 252 * @ahci_dev: AHCI parent device 253 * @devp: Returns new SCSI bus device 254 * @return 0 if OK, -ve on error 255 */ 256 int ahci_bind_scsi(struct rt_device *ahci_dev, struct rt_device **devp); 257 258 /** 259 * ahci_probe_scsi() - probe and scan the attached SCSI bus 260 * 261 * Note that the SCSI device will itself bind block devices for any storage 262 * devices it finds. 263 * 264 * @ahci_dev: AHCI parent device 265 * @base: Base address of AHCI port 266 * @return 0 if OK, -ve on error 267 */ 268 int ahci_probe_scsi(struct rt_device *ahci_dev, ulong base); 269 270 /** 271 * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI 272 * 273 * Note that the SCSI device will itself bind block devices for any storage 274 * devices it finds. 275 * 276 * @ahci_dev: AHCI parent device 277 * @return 0 if OK, -ve on error 278 */ 279 int ahci_probe_scsi_pci(struct rt_device *ahci_dev); 280 281 #endif 282