1 /* 2 * Copyright (c) 2006-2020, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2020-04-05 bigmagic Initial version 9 */ 10 11 #ifndef _DRV_UART_H__ 12 #define _DRV_UART_H__ 13 14 #include "ls2k1000.h" 15 #include <rthw.h> 16 17 /* UART registers */ 18 #define UART_DAT(base) HWREG8(base + 0x00) 19 #define UART_IER(base) HWREG8(base + 0x01) 20 #define UART_IIR(base) HWREG8(base + 0x02) 21 #define UART_FCR(base) HWREG8(base + 0x02) 22 #define UART_LCR(base) HWREG8(base + 0x03) 23 #define UART_MCR(base) HWREG8(base + 0x04) 24 #define UART_LSR(base) HWREG8(base + 0x05) 25 #define UART_MSR(base) HWREG8(base + 0x06) 26 27 #define UART_LSB(base) HWREG8(base + 0x00) 28 #define UART_MSB(base) HWREG8(base + 0x01) 29 30 /* interrupt enable register */ 31 #define IER_IRxE 0x1 32 #define IER_ITxE 0x2 33 #define IER_ILE 0x4 34 #define IER_IME 0x8 35 36 /* interrupt identification register */ 37 #define IIR_IMASK 0xf /* mask */ 38 #define IIR_RXTOUT 0xc /* receive timeout */ 39 #define IIR_RLS 0x6 /* receive line status */ 40 #define IIR_RXRDY 0x4 /* receive ready */ 41 #define IIR_TXRDY 0x2 /* transmit ready */ 42 #define IIR_NOPEND 0x1 /* nothing */ 43 #define IIR_MLSC 0x0 /* modem status */ 44 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 45 46 /* fifo control register */ 47 #define FIFO_ENABLE 0x01 /* enable fifo */ 48 #define FIFO_RCV_RST 0x02 /* reset receive fifo */ 49 #define FIFO_XMT_RST 0x04 /* reset transmit fifo */ 50 #define FIFO_DMA_MODE 0x08 /* enable dma mode */ 51 #define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */ 52 #define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */ 53 #define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */ 54 #define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */ 55 56 /* character format control register */ 57 #define CFCR_DLAB 0x80 /* divisor latch */ 58 #define CFCR_SBREAK 0x40 /* send break */ 59 #define CFCR_PZERO 0x30 /* zero parity */ 60 #define CFCR_PONE 0x20 /* one parity */ 61 #define CFCR_PEVEN 0x10 /* even parity */ 62 #define CFCR_PODD 0x00 /* odd parity */ 63 #define CFCR_PENAB 0x08 /* parity enable */ 64 #define CFCR_STOPB 0x04 /* 2 stop bits */ 65 #define CFCR_8BITS 0x03 /* 8 data bits */ 66 #define CFCR_7BITS 0x02 /* 7 data bits */ 67 #define CFCR_6BITS 0x01 /* 6 data bits */ 68 #define CFCR_5BITS 0x00 /* 5 data bits */ 69 70 /* modem control register */ 71 #define MCR_LOOPBACK 0x10 /* loopback */ 72 #define MCR_IENABLE 0x08 /* output 2 = int enable */ 73 #define MCR_DRS 0x04 /* output 1 = xxx */ 74 #define MCR_RTS 0x02 /* enable RTS */ 75 #define MCR_DTR 0x01 /* enable DTR */ 76 77 /* line status register */ 78 #define LSR_RCV_FIFO 0x80 /* error in receive fifo */ 79 #define LSR_TSRE 0x40 /* transmitter empty */ 80 #define LSR_TXRDY 0x20 /* transmitter ready */ 81 #define LSR_BI 0x10 /* break detected */ 82 #define LSR_FE 0x08 /* framing error */ 83 #define LSR_PE 0x04 /* parity error */ 84 #define LSR_OE 0x02 /* overrun error */ 85 #define LSR_RXRDY 0x01 /* receiver ready */ 86 #define LSR_RCV_MASK 0x1f 87 88 89 /* UART interrupt enable register value */ 90 #define UARTIER_IME (1 << 3) 91 #define UARTIER_ILE (1 << 2) 92 #define UARTIER_ITXE (1 << 1) 93 #define UARTIER_IRXE (1 << 0) 94 95 /* UART line control register value */ 96 #define UARTLCR_DLAB (1 << 7) 97 #define UARTLCR_BCB (1 << 6) 98 #define UARTLCR_SPB (1 << 5) 99 #define UARTLCR_EPS (1 << 4) 100 #define UARTLCR_PE (1 << 3) 101 #define UARTLCR_SB (1 << 2) 102 103 /* UART line status register value */ 104 #define UARTLSR_ERROR (1 << 7) 105 #define UARTLSR_TE (1 << 6) 106 #define UARTLSR_TFE (1 << 5) 107 #define UARTLSR_BI (1 << 4) 108 #define UARTLSR_FE (1 << 3) 109 #define UARTLSR_PE (1 << 2) 110 #define UARTLSR_OE (1 << 1) 111 #define UARTLSR_DR (1 << 0) 112 113 #endif 114