1 #ifndef _LS2K1000_H__
2 #define _LS2K1000_H__
3 
4 #include <mips.h>
5 #include "interrupt.h"
6 #include <rthw.h>
7 
8 #define APB_BASE         CKSEG1ADDR(0xbfe00000)
9 
10 #define UART0_BASE_ADDR  (0xbfe00000)
11 #define UART0_OFF        (0x0)
12 #define UART0_BASE       CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
13 
14 #define UARTx_BASE(x)    ((APB_BASE | (0x0 << 12) | (x << 8)))
15 
16 #define LIOINTC0_BASE    CKSEG1ADDR(0x1fe11400)
17 #define CORE0_INTISR0    CKSEG1ADDR(0x1fe11040)
18 
19 #define LIOINTC1_BASE    CKSEG1ADDR(0x1fe11440)
20 #define CORE0_INTISR1    CKSEG1ADDR(0x1fe11048)
21 
22 #define GPIO_BASE        (0xFFFFFFFFBFE10500)
23 #define PLL_SYS_BASE     (0xFFFFFFFFBFE10480)
24 #define RTC_BASE         (0xFFFFFFFFBFE07820)
25 
26 #define GEN_CONFIG0_REG  (0xFFFFFFFFBfe10420)
27 
28 
29 /*
30  * General PM Configuration Register
31  */
32 #define PMCON_BASE          (APB_BASE | (0x7 << 12))
33 
34 /*
35  * Power Management1 Configuration Registers
36  */
37 #define PM1_BASE            (PMCON_BASE + 0x0C)
38 #define PM1_STS             HWREG32(PM1_BASE)
39 #define PM1_EN              HWREG32(PM1_BASE + 0x04)
40 #define PM1_CNT             HWREG32(PM1_BASE + 0x08)
41 
42 /*
43  * Watch Dog Configuration Registers
44  */
45 #define WDT_BASE            (PMCON_BASE + 0x30)
46 #define WDT_EN              HWREG32(WDT_BASE)
47 #define WDT_SET             HWREG32(WDT_BASE + 0x04)
48 #define WDT_TIMER           HWREG32(WDT_BASE + 0x08)
49 
50 void rt_hw_timer_handler(void);
51 void rt_hw_uart_init(void);
52 
53 #endif
54 
55