1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2010-04-09 fify the first version
9 *
10 * For : Renesas M16C
11 * Toolchain : IAR's EW for M16C v3.401
12 */
13
14 #include "iom16c62p.h"
15 #include "bsp.h"
16 #include "rtconfig.h"
17
led_init(void)18 void led_init(void)
19 {
20 PUR3.BIT.PU37 = 1;
21 PD11.BIT.PD11_0 = 1;
22
23 led_off();
24 }
25
led_on(void)26 void led_on(void)
27 {
28 P11.BIT.P11_0 = 0;
29 }
30
led_off(void)31 void led_off(void)
32 {
33 P11.BIT.P11_0 = 1;
34 }
35
mcu_init(void)36 static void mcu_init(void)
37 {
38 volatile rt_uint32_t count;
39 /* Configure clock for divide by 1 mode */
40 PRCR.BYTE |= 0x01; /* Enable access to clock registers PRCR.PRC0 = 1 */
41 CM1.BYTE = 0x20; /* Set CM16, CM17 divide ratio to 1: */
42 /* ... main clock on in high drive no PLL */
43 CM0.BYTE &= ~0x40; /* Set divide ratio to 1 CM0.CM06 = 0 */
44
45 /* Configure main PLL */
46 PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */
47 PM2.BYTE |= 0x01; /* Set SFR access to 2 wait, which is required for */
48 /* ... operation greater than 16 MHz PM2.PM20 = 1 */
49 PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */
50 PLC0.BYTE = 0x91; /* Enable and turn on PLL */
51
52 count = 20000; /* Delay while PLL stabilizes */
53 while (count > 0) {
54 count--;
55 }
56
57 CM1.BYTE |= 0x02; /* Switch to PLL CM1.CM11 = 1 */
58 PRCR.BYTE &= ~0x01; /* Protect clock control register PRCR.PRC0 = 0 */
59
60 PRCR.BYTE |= 0x02; /* Allow writing to processor mode register PRCR.PRC0 = 1 */
61 PM1.BYTE |= 0x01; /* Enable data flash area PM1.PM10 = 1 */
62 PRCR.BYTE &= ~0x02; /* Protect processor mode register PRCR.PRC0 = 0 */
63 }
64
65 /*
66 *********************************************************************************************************
67 * TICKER INITIALIZATION
68 *
69 * Description : This function is called to initialize rt-thread's tick source (typically a timer generating
70 * interrupts every 1 to 100 mS).
71 *
72 * We decided to use Timer #B0 as the tick interrupt source.
73 *
74 * Arguments : none
75 *
76 * Returns :
77 *
78 * Notes : (1) Timer B channel 0 is setup as a periodic timer, generating an interrupt
79 * OS_TICKS_PER_SEC times per second. The timer counts down and generates an interrupt
80 * when it underflows.
81 *
82 * (2) The timer ISR handler, rt_hw_timer_handler(), is placed into the vector table in vectors.s34.
83 *********************************************************************************************************
84 */
85
timer_tick_init(void)86 static void timer_tick_init(void)
87 {
88 /* Set timer to timer mode */
89 /* Set count source as PLL clock / 8 (f8) */
90 TB0MR.BYTE = 0x40;
91 /* Assign timer value and reload value */
92 TB0 = (CPU_CLK_FREQ / 8) / RT_TICK_PER_SECOND;
93 /* Set timer B channel 0 interrupt level = 7 */
94 /* Clear interrupt request */
95 TB0IC.BYTE = 0x07;
96 TABSR.BYTE |= 0x20; /* Start timer */
97 }
98
system_init(void)99 void system_init(void)
100 {
101 mcu_init();
102 led_init(); /* Initialize the I/Os for the LED controls */
103 timer_tick_init(); /* Initialize the rt-thread tick interrupt */
104 }
105