1 /** 2 * @file rtc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 4 */ 5 6 /* **************************************************************************** 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included 17 * in all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 * Except as contained in this notice, the name of Maxim Integrated 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated 29 * Products, Inc. Branding Policy. 30 * 31 * The mere transfer of this software does not imply any licenses 32 * of trade secrets, proprietary technology, copyrights, patents, 33 * trademarks, maskwork rights, or any other form of intellectual 34 * property whatsoever. Maxim Integrated Products, Inc. retains all 35 * ownership rights. 36 * 37 * 38 *************************************************************************** */ 39 40 #ifndef _RTC_REGS_H_ 41 #define _RTC_REGS_H_ 42 43 /* **** Includes **** */ 44 #include <stdint.h> 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 #if defined (__ICCARM__) 51 #pragma system_include 52 #endif 53 54 #if defined (__CC_ARM) 55 #pragma anon_unions 56 #endif 57 /// @cond 58 /* 59 If types are not defined elsewhere (CMSIS) define them here 60 */ 61 #ifndef __IO 62 #define __IO volatile 63 #endif 64 #ifndef __I 65 #define __I volatile const 66 #endif 67 #ifndef __O 68 #define __O volatile 69 #endif 70 #ifndef __R 71 #define __R volatile const 72 #endif 73 /// @endcond 74 75 /* **** Definitions **** */ 76 77 /** 78 * @ingroup rtc 79 * @defgroup rtc_registers RTC_Registers 80 * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. 81 * @details Real Time Clock and Alarm. 82 */ 83 84 /** 85 * @ingroup rtc_registers 86 * Structure type to access the RTC Registers. 87 */ 88 typedef struct { 89 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */ 90 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */ 91 __IO uint32_t ras; /**< <tt>\b 0x08:</tt> RTC RAS Register */ 92 __IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> RTC RSSA Register */ 93 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */ 94 __IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */ 95 __IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */ 96 } mxc_rtc_regs_t; 97 98 /* Register offsets for module RTC */ 99 /** 100 * @ingroup rtc_registers 101 * @defgroup RTC_Register_Offsets Register Offsets 102 * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. 103 * @{ 104 */ 105 #define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */ 112 /**@} end of group rtc_registers */ 113 114 /** 115 * @ingroup rtc_registers 116 * @defgroup RTC_SSEC RTC_SSEC 117 * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented 118 * when this register rolls over from 0xFF to 0x00. 119 * @{ 120 */ 121 #define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ 122 #define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ 123 124 /**@} end of group RTC_SSEC_Register */ 125 126 /** 127 * @ingroup rtc_registers 128 * @defgroup RTC_RAS RTC_RAS 129 * @brief Time-of-day Alarm. 130 * @{ 131 */ 132 #define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */ 133 #define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */ 134 135 /**@} end of group RTC_RAS_Register */ 136 137 /** 138 * @ingroup rtc_registers 139 * @defgroup RTC_RSSA RTC_RSSA 140 * @brief RTC sub-second alarm. This register contains the reload value for the sub- 141 * second alarm. 142 * @{ 143 */ 144 #define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ 145 #define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ 146 147 /**@} end of group RTC_RSSA_Register */ 148 149 /** 150 * @ingroup rtc_registers 151 * @defgroup RTC_CTRL RTC_CTRL 152 * @brief RTC Control Register. 153 * @{ 154 */ 155 #define MXC_F_RTC_CTRL_RTCE_POS 0 /**< CTRL_RTCE Position */ 156 #define MXC_F_RTC_CTRL_RTCE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RTCE_POS)) /**< CTRL_RTCE Mask */ 157 #define MXC_V_RTC_CTRL_RTCE_DIS ((uint32_t)0x0UL) /**< CTRL_RTCE_DIS Value */ 158 #define MXC_S_RTC_CTRL_RTCE_DIS (MXC_V_RTC_CTRL_RTCE_DIS << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_DIS Setting */ 159 #define MXC_V_RTC_CTRL_RTCE_EN ((uint32_t)0x1UL) /**< CTRL_RTCE_EN Value */ 160 #define MXC_S_RTC_CTRL_RTCE_EN (MXC_V_RTC_CTRL_RTCE_EN << MXC_F_RTC_CTRL_RTCE_POS) /**< CTRL_RTCE_EN Setting */ 161 162 #define MXC_F_RTC_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ 163 #define MXC_F_RTC_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ 164 #define MXC_V_RTC_CTRL_ADE_DIS ((uint32_t)0x0UL) /**< CTRL_ADE_DIS Value */ 165 #define MXC_S_RTC_CTRL_ADE_DIS (MXC_V_RTC_CTRL_ADE_DIS << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_DIS Setting */ 166 #define MXC_V_RTC_CTRL_ADE_EN ((uint32_t)0x1UL) /**< CTRL_ADE_EN Value */ 167 #define MXC_S_RTC_CTRL_ADE_EN (MXC_V_RTC_CTRL_ADE_EN << MXC_F_RTC_CTRL_ADE_POS) /**< CTRL_ADE_EN Setting */ 168 169 #define MXC_F_RTC_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ 170 #define MXC_F_RTC_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ 171 #define MXC_V_RTC_CTRL_ASE_DIS ((uint32_t)0x0UL) /**< CTRL_ASE_DIS Value */ 172 #define MXC_S_RTC_CTRL_ASE_DIS (MXC_V_RTC_CTRL_ASE_DIS << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_DIS Setting */ 173 #define MXC_V_RTC_CTRL_ASE_EN ((uint32_t)0x1UL) /**< CTRL_ASE_EN Value */ 174 #define MXC_S_RTC_CTRL_ASE_EN (MXC_V_RTC_CTRL_ASE_EN << MXC_F_RTC_CTRL_ASE_POS) /**< CTRL_ASE_EN Setting */ 175 176 #define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 177 #define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 178 #define MXC_V_RTC_CTRL_BUSY_IDLE ((uint32_t)0x0UL) /**< CTRL_BUSY_IDLE Value */ 179 #define MXC_S_RTC_CTRL_BUSY_IDLE (MXC_V_RTC_CTRL_BUSY_IDLE << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_IDLE Setting */ 180 #define MXC_V_RTC_CTRL_BUSY_BUSY ((uint32_t)0x1UL) /**< CTRL_BUSY_BUSY Value */ 181 #define MXC_S_RTC_CTRL_BUSY_BUSY (MXC_V_RTC_CTRL_BUSY_BUSY << MXC_F_RTC_CTRL_BUSY_POS) /**< CTRL_BUSY_BUSY Setting */ 182 183 #define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 184 #define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 185 #define MXC_V_RTC_CTRL_RDY_BUSY ((uint32_t)0x0UL) /**< CTRL_RDY_BUSY Value */ 186 #define MXC_S_RTC_CTRL_RDY_BUSY (MXC_V_RTC_CTRL_RDY_BUSY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_BUSY Setting */ 187 #define MXC_V_RTC_CTRL_RDY_READY ((uint32_t)0x1UL) /**< CTRL_RDY_READY Value */ 188 #define MXC_S_RTC_CTRL_RDY_READY (MXC_V_RTC_CTRL_RDY_READY << MXC_F_RTC_CTRL_RDY_POS) /**< CTRL_RDY_READY Setting */ 189 190 #define MXC_F_RTC_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ 191 #define MXC_F_RTC_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ 192 #define MXC_V_RTC_CTRL_RDYE_DIS ((uint32_t)0x0UL) /**< CTRL_RDYE_DIS Value */ 193 #define MXC_S_RTC_CTRL_RDYE_DIS (MXC_V_RTC_CTRL_RDYE_DIS << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_DIS Setting */ 194 #define MXC_V_RTC_CTRL_RDYE_EN ((uint32_t)0x1UL) /**< CTRL_RDYE_EN Value */ 195 #define MXC_S_RTC_CTRL_RDYE_EN (MXC_V_RTC_CTRL_RDYE_EN << MXC_F_RTC_CTRL_RDYE_POS) /**< CTRL_RDYE_EN Setting */ 196 197 #define MXC_F_RTC_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ 198 #define MXC_F_RTC_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ 199 #define MXC_V_RTC_CTRL_ALDF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALDF_INACTIVE Value */ 200 #define MXC_S_RTC_CTRL_ALDF_INACTIVE (MXC_V_RTC_CTRL_ALDF_INACTIVE << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_INACTIVE Setting */ 201 #define MXC_V_RTC_CTRL_ALDF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALDF_PENDING Value */ 202 #define MXC_S_RTC_CTRL_ALDF_PENDING (MXC_V_RTC_CTRL_ALDF_PENDING << MXC_F_RTC_CTRL_ALDF_POS) /**< CTRL_ALDF_PENDING Setting */ 203 204 #define MXC_F_RTC_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ 205 #define MXC_F_RTC_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ 206 #define MXC_V_RTC_CTRL_ALSF_INACTIVE ((uint32_t)0x0UL) /**< CTRL_ALSF_INACTIVE Value */ 207 #define MXC_S_RTC_CTRL_ALSF_INACTIVE (MXC_V_RTC_CTRL_ALSF_INACTIVE << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_INACTIVE Setting */ 208 #define MXC_V_RTC_CTRL_ALSF_PENDING ((uint32_t)0x1UL) /**< CTRL_ALSF_PENDING Value */ 209 #define MXC_S_RTC_CTRL_ALSF_PENDING (MXC_V_RTC_CTRL_ALSF_PENDING << MXC_F_RTC_CTRL_ALSF_POS) /**< CTRL_ALSF_PENDING Setting */ 210 211 #define MXC_F_RTC_CTRL_SQE_POS 8 /**< CTRL_SQE Position */ 212 #define MXC_F_RTC_CTRL_SQE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQE_POS)) /**< CTRL_SQE Mask */ 213 #define MXC_V_RTC_CTRL_SQE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_SQE_INACTIVE Value */ 214 #define MXC_S_RTC_CTRL_SQE_INACTIVE (MXC_V_RTC_CTRL_SQE_INACTIVE << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_INACTIVE Setting */ 215 #define MXC_V_RTC_CTRL_SQE_PENDING ((uint32_t)0x1UL) /**< CTRL_SQE_PENDING Value */ 216 #define MXC_S_RTC_CTRL_SQE_PENDING (MXC_V_RTC_CTRL_SQE_PENDING << MXC_F_RTC_CTRL_SQE_POS) /**< CTRL_SQE_PENDING Setting */ 217 218 #define MXC_F_RTC_CTRL_FT_POS 9 /**< CTRL_FT Position */ 219 #define MXC_F_RTC_CTRL_FT ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_FT_POS)) /**< CTRL_FT Mask */ 220 #define MXC_V_RTC_CTRL_FT_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_FT_FREQ1HZ Value */ 221 #define MXC_S_RTC_CTRL_FT_FREQ1HZ (MXC_V_RTC_CTRL_FT_FREQ1HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ1HZ Setting */ 222 #define MXC_V_RTC_CTRL_FT_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_FT_FREQ512HZ Value */ 223 #define MXC_S_RTC_CTRL_FT_FREQ512HZ (MXC_V_RTC_CTRL_FT_FREQ512HZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ512HZ Setting */ 224 #define MXC_V_RTC_CTRL_FT_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_FT_FREQ4KHZ Value */ 225 #define MXC_S_RTC_CTRL_FT_FREQ4KHZ (MXC_V_RTC_CTRL_FT_FREQ4KHZ << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_FREQ4KHZ Setting */ 226 #define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */ 227 #define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */ 228 229 #define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */ 230 #define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */ 231 #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */ 232 #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */ 233 #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */ 234 #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */ 235 #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */ 236 #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */ 237 #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */ 238 #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */ 239 240 #define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */ 241 #define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */ 242 #define MXC_V_RTC_CTRL_WE_INACTIVE ((uint32_t)0x0UL) /**< CTRL_WE_INACTIVE Value */ 243 #define MXC_S_RTC_CTRL_WE_INACTIVE (MXC_V_RTC_CTRL_WE_INACTIVE << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_INACTIVE Setting */ 244 #define MXC_V_RTC_CTRL_WE_PENDING ((uint32_t)0x1UL) /**< CTRL_WE_PENDING Value */ 245 #define MXC_S_RTC_CTRL_WE_PENDING (MXC_V_RTC_CTRL_WE_PENDING << MXC_F_RTC_CTRL_WE_POS) /**< CTRL_WE_PENDING Setting */ 246 247 /**@} end of group RTC_CTRL_Register */ 248 249 /** 250 * @ingroup rtc_registers 251 * @defgroup RTC_TRIM RTC_TRIM 252 * @brief RTC Trim Register. 253 * @{ 254 */ 255 #define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ 256 #define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ 257 258 #define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */ 259 #define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */ 260 261 /**@} end of group RTC_TRIM_Register */ 262 263 /** 264 * @ingroup rtc_registers 265 * @defgroup RTC_OSCCTRL RTC_OSCCTRL 266 * @brief RTC Oscillator Control Register. 267 * @{ 268 */ 269 #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */ 270 #define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */ 271 272 #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ 273 #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ 274 #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X ((uint32_t)0x0UL) /**< OSCCTRL_IBIAS_SEL_2X Value */ 275 #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_2X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_2X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_2X Setting */ 276 #define MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X ((uint32_t)0x1UL) /**< OSCCTRL_IBIAS_SEL_4X Value */ 277 #define MXC_S_RTC_OSCCTRL_IBIAS_SEL_4X (MXC_V_RTC_OSCCTRL_IBIAS_SEL_4X << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS) /**< OSCCTRL_IBIAS_SEL_4X Setting */ 278 279 #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ 280 #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ 281 282 #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ 283 #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ 284 285 #define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ 286 #define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ 287 288 #define MXC_F_RTC_OSCCTRL_OUT32K_POS 5 /**< OSCCTRL_OUT32K Position */ 289 #define MXC_F_RTC_OSCCTRL_OUT32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_OUT32K_POS)) /**< OSCCTRL_OUT32K Mask */ 290 291 /**@} end of group RTC_OSCCTRL_Register */ 292 293 #ifdef __cplusplus 294 } 295 #endif 296 297 #endif /* _RTC_REGS_H_ */ 298