1 /** 2 * \file 3 * 4 * \brief SPI related functionality declaration. 5 * 6 * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Subject to your compliance with these terms, you may use Microchip 13 * software and any derivatives exclusively with Microchip products. 14 * It is your responsibility to comply with third party license terms applicable 15 * to your use of third party software (including open source software) that 16 * may accompany Microchip software. 17 * 18 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 * 30 * \asf_license_stop 31 * 32 */ 33 34 #ifndef _HPL_SPI_S_SYNC_H_INCLUDED 35 #define _HPL_SPI_S_SYNC_H_INCLUDED 36 37 #include <hpl_spi_sync.h> 38 39 /** 40 * \addtogroup hpl_spi HPL SPI 41 * 42 *@{ 43 */ 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /** Uses common SPI sync device driver. */ 50 #define _spi_s_sync_dev _spi_sync_dev 51 52 /** 53 * \name HPL functions 54 */ 55 //@{ 56 /** 57 * \brief Initialize SPI for access without interrupts 58 * It will load default hardware configuration and software struct. 59 * \param[in, out] dev Pointer to the SPI device instance. 60 * \param[in] hw Pointer to the hardware base. 61 * \return Operation status. 62 * \retval ERR_INVALID_ARG Input parameter problem. 63 * \retval ERR_BUSY SPI hardware not ready (resetting). 64 * \retval ERR_DENIED SPI has been enabled. 65 * \retval 0 Operation done successfully. 66 */ 67 int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); 68 69 /** 70 * \brief Initialize SPI for access with interrupts 71 * Disable, reset the hardware and the software struct. 72 * \param[in, out] dev Pointer to the SPI device instance. 73 * \return Operation status. 74 * \retval 0 Operation done successfully. 75 */ 76 int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); 77 78 /** 79 * \brief Enable SPI for access without interrupts 80 * \param[in, out] dev Pointer to the SPI device instance. 81 * \return Operation status. 82 * \retval ERR_BUSY SPI hardware not ready (resetting). 83 * \retval 0 Operation done successfully. 84 */ 85 int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); 86 87 /** 88 * \brief Disable SPI for access without interrupts 89 * Disable SPI. Deactivate all CS pins if works as master. 90 * \param[in, out] dev Pointer to the SPI device instance. 91 * \return Operation status. 92 * \retval 0 Operation done successfully. 93 */ 94 int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); 95 96 /** 97 * \brief Set SPI transfer mode 98 * Set SPI transfer mode (\ref spi_transfer_mode), 99 * which controls clock polarity and clock phase. 100 * Mode 0: leading edge is rising edge, data sample on leading edge. 101 * Mode 1: leading edge is rising edge, data sample on trailing edge. 102 * Mode 2: leading edge is falling edge, data sample on leading edge. 103 * Mode 3: leading edge is falling edge, data sample on trailing edge. 104 * \param[in, out] dev Pointer to the SPI device instance. 105 * \param[in] mode The SPI transfer mode. 106 * \return Operation status. 107 * \retval ERR_BUSY SPI is not ready to accept new setting. 108 * \retval 0 Operation done successfully. 109 */ 110 int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); 111 112 /** 113 * \brief Set SPI baudrate 114 * \param[in, out] dev Pointer to the SPI device instance. 115 * \param[in] char_size The character size, see \ref spi_char_size. 116 * \return Operation status. 117 * \retval ERR_INVALID_ARG The character size is not supported. 118 * \retval ERR_BUSY SPI is not ready to accept new setting. 119 * \retval 0 Operation done successfully. 120 */ 121 int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); 122 123 /** 124 * \brief Set SPI data order 125 * \param[in, out] dev Pointer to the SPI device instance. 126 * \param[in] dord SPI data order (LSB/MSB first). 127 * \return Operation status. 128 * \retval ERR_INVALID_ARG The character size is not supported. 129 * \retval ERR_BUSY SPI is not ready to accept new setting. 130 * \retval 0 Operation done successfully. 131 */ 132 int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); 133 134 /** 135 * \brief Enable interrupt on character output 136 * 137 * Enable interrupt when a new character can be written 138 * to the SPI device. 139 * 140 * \param[in] dev Pointer to the SPI device instance 141 * \param[in] state true = enable output interrupt 142 * false = disable output interrupt 143 * 144 * \return Status code 145 * \retval 0 Ok status 146 */ 147 int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); 148 149 /** 150 * \brief Enable interrupt on character input 151 * 152 * Enable interrupt when a new character is ready to be 153 * read from the SPI device. 154 * 155 * \param[in] dev Pointer to the SPI device instance 156 * \param[in] state true = enable input interrupts 157 * false = disable input interrupt 158 * 159 * \return Status code 160 * \retval 0 OK Status 161 */ 162 int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); 163 164 /** 165 * \brief Read one character to SPI device instance 166 * \param[in, out] dev Pointer to the SPI device instance. 167 * 168 * \return Character read from SPI module 169 */ 170 uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); 171 172 /** 173 * \brief Write one character to assigned buffer 174 * \param[in, out] dev Pointer to the SPI device instance. 175 * \param[in] data 176 * 177 * \return Status code of write operation 178 * \retval 0 Write operation OK 179 */ 180 int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); 181 182 /** 183 * \brief Check if TX ready 184 * 185 * \param[in] dev Pointer to the SPI device instance 186 * 187 * \return TX ready state 188 * \retval true TX ready 189 * \retval false TX not ready 190 */ 191 bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); 192 193 /** 194 * \brief Check if RX character ready 195 * 196 * \param[in] dev Pointer to the SPI device instance 197 * 198 * \return RX character ready state 199 * \retval true RX character ready 200 * \retval false RX character not ready 201 */ 202 bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); 203 204 /** 205 * \brief Check if SS deactiviation detected 206 * 207 * \param[in] dev Pointer to the SPI device instance 208 * 209 * \return SS deactiviation state 210 * \retval true SS deactiviation detected 211 * \retval false SS deactiviation not detected 212 */ 213 bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); 214 215 /** 216 * \brief Check if error is detected 217 * 218 * \param[in] dev Pointer to the SPI device instance 219 * 220 * \return Error detection state 221 * \retval true Error detected 222 * \retval false Error not detected 223 */ 224 bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); 225 //@} 226 227 #ifdef __cplusplus 228 } 229 #endif 230 231 /**@}*/ 232 #endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ 233