1 /** 2 * \file 3 * 4 * \brief Component description for GCLK 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_GCLK_COMPONENT_ 31 #define _SAMC21_GCLK_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR GCLK */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_GCLK Generic Clock Generator */ 37 /*@{*/ 38 39 #define GCLK_U2122 40 #define REV_GCLK 0x111 41 42 /* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 48 } bit; /*!< Structure used for bit access */ 49 uint8_t reg; /*!< Type used for register access */ 50 } GCLK_CTRLA_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */ 54 #define GCLK_CTRLA_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRLA reset_value) Control */ 55 56 #define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */ 57 #define GCLK_CTRLA_SWRST (_U_(0x1) << GCLK_CTRLA_SWRST_Pos) 58 #define GCLK_CTRLA_MASK _U_(0x01) /**< \brief (GCLK_CTRLA) MASK Register */ 59 60 /* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */ 61 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 62 typedef union { 63 struct { 64 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */ 65 uint32_t :1; /*!< bit: 1 Reserved */ 66 uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */ 67 uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */ 68 uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */ 69 uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */ 70 uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */ 71 uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */ 72 uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */ 73 uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */ 74 uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */ 75 uint32_t :21; /*!< bit: 11..31 Reserved */ 76 } bit; /*!< Structure used for bit access */ 77 struct { 78 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 79 uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control x Synchronization Busy bits */ 80 uint32_t :21; /*!< bit: 11..31 Reserved */ 81 } vec; /*!< Structure used for vec access */ 82 uint32_t reg; /*!< Type used for register access */ 83 } GCLK_SYNCBUSY_Type; 84 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 85 86 #define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */ 87 #define GCLK_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */ 88 89 #define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */ 90 #define GCLK_SYNCBUSY_SWRST (_U_(0x1) << GCLK_SYNCBUSY_SWRST_Pos) 91 #define GCLK_SYNCBUSY_GENCTRL0_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 0 Synchronization Busy bits */ 92 #define GCLK_SYNCBUSY_GENCTRL0 (_U_(1) << GCLK_SYNCBUSY_GENCTRL0_Pos) 93 #define GCLK_SYNCBUSY_GENCTRL1_Pos 3 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 1 Synchronization Busy bits */ 94 #define GCLK_SYNCBUSY_GENCTRL1 (_U_(1) << GCLK_SYNCBUSY_GENCTRL1_Pos) 95 #define GCLK_SYNCBUSY_GENCTRL2_Pos 4 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 2 Synchronization Busy bits */ 96 #define GCLK_SYNCBUSY_GENCTRL2 (_U_(1) << GCLK_SYNCBUSY_GENCTRL2_Pos) 97 #define GCLK_SYNCBUSY_GENCTRL3_Pos 5 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 3 Synchronization Busy bits */ 98 #define GCLK_SYNCBUSY_GENCTRL3 (_U_(1) << GCLK_SYNCBUSY_GENCTRL3_Pos) 99 #define GCLK_SYNCBUSY_GENCTRL4_Pos 6 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 4 Synchronization Busy bits */ 100 #define GCLK_SYNCBUSY_GENCTRL4 (_U_(1) << GCLK_SYNCBUSY_GENCTRL4_Pos) 101 #define GCLK_SYNCBUSY_GENCTRL5_Pos 7 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 5 Synchronization Busy bits */ 102 #define GCLK_SYNCBUSY_GENCTRL5 (_U_(1) << GCLK_SYNCBUSY_GENCTRL5_Pos) 103 #define GCLK_SYNCBUSY_GENCTRL6_Pos 8 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 6 Synchronization Busy bits */ 104 #define GCLK_SYNCBUSY_GENCTRL6 (_U_(1) << GCLK_SYNCBUSY_GENCTRL6_Pos) 105 #define GCLK_SYNCBUSY_GENCTRL7_Pos 9 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 7 Synchronization Busy bits */ 106 #define GCLK_SYNCBUSY_GENCTRL7 (_U_(1) << GCLK_SYNCBUSY_GENCTRL7_Pos) 107 #define GCLK_SYNCBUSY_GENCTRL8_Pos 10 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control 8 Synchronization Busy bits */ 108 #define GCLK_SYNCBUSY_GENCTRL8 (_U_(1) << GCLK_SYNCBUSY_GENCTRL8_Pos) 109 #define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control x Synchronization Busy bits */ 110 #define GCLK_SYNCBUSY_GENCTRL_Msk (_U_(0x1FF) << GCLK_SYNCBUSY_GENCTRL_Pos) 111 #define GCLK_SYNCBUSY_GENCTRL(value) (GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos)) 112 #define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val _U_(0x1) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */ 113 #define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val _U_(0x2) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */ 114 #define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val _U_(0x4) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */ 115 #define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val _U_(0x8) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */ 116 #define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val _U_(0x10) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */ 117 #define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val _U_(0x20) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */ 118 #define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val _U_(0x40) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */ 119 #define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val _U_(0x80) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */ 120 #define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val _U_(0x100) /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */ 121 #define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 122 #define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 123 #define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 124 #define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 125 #define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 126 #define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 127 #define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 128 #define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 129 #define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos) 130 #define GCLK_SYNCBUSY_MASK _U_(0x000007FD) /**< \brief (GCLK_SYNCBUSY) MASK Register */ 131 132 /* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */ 133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 134 typedef union { 135 struct { 136 uint32_t SRC:3; /*!< bit: 0.. 2 Source Select */ 137 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 138 uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */ 139 uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */ 140 uint32_t OOV:1; /*!< bit: 10 Output Off Value */ 141 uint32_t OE:1; /*!< bit: 11 Output Enable */ 142 uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */ 143 uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */ 144 uint32_t :2; /*!< bit: 14..15 Reserved */ 145 uint32_t DIV:16; /*!< bit: 16..31 Division Factor */ 146 } bit; /*!< Structure used for bit access */ 147 uint32_t reg; /*!< Type used for register access */ 148 } GCLK_GENCTRL_Type; 149 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 150 151 #define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ 152 #define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ 153 154 #define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */ 155 #define GCLK_GENCTRL_SRC_Msk (_U_(0x7) << GCLK_GENCTRL_SRC_Pos) 156 #define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)) 157 #define GCLK_GENCTRL_SRC_XOSC_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ 158 #define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) Generator input pad */ 159 #define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ 160 #define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ 161 #define GCLK_GENCTRL_SRC_OSC32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ 162 #define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ 163 #define GCLK_GENCTRL_SRC_OSC48M_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) OSC48M oscillator output */ 164 #define GCLK_GENCTRL_SRC_DPLL96M_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DPLL96M output */ 165 #define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) 166 #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) 167 #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) 168 #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) 169 #define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) 170 #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) 171 #define GCLK_GENCTRL_SRC_OSC48M (GCLK_GENCTRL_SRC_OSC48M_Val << GCLK_GENCTRL_SRC_Pos) 172 #define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos) 173 #define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ 174 #define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos) 175 #define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ 176 #define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos) 177 #define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */ 178 #define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos) 179 #define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */ 180 #define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos) 181 #define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */ 182 #define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos) 183 #define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */ 184 #define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos) 185 #define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */ 186 #define GCLK_GENCTRL_DIV_Msk (_U_(0xFFFF) << GCLK_GENCTRL_DIV_Pos) 187 #define GCLK_GENCTRL_DIV(value) (GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos)) 188 #define GCLK_GENCTRL_MASK _U_(0xFFFF3F07) /**< \brief (GCLK_GENCTRL) MASK Register */ 189 190 /* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */ 191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 192 typedef union { 193 struct { 194 uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */ 195 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 196 uint32_t CHEN:1; /*!< bit: 6 Channel Enable */ 197 uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */ 198 uint32_t :24; /*!< bit: 8..31 Reserved */ 199 } bit; /*!< Structure used for bit access */ 200 uint32_t reg; /*!< Type used for register access */ 201 } GCLK_PCHCTRL_Type; 202 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 203 204 #define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */ 205 #define GCLK_PCHCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */ 206 207 #define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */ 208 #define GCLK_PCHCTRL_GEN_Msk (_U_(0xF) << GCLK_PCHCTRL_GEN_Pos) 209 #define GCLK_PCHCTRL_GEN(value) (GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos)) 210 #define GCLK_PCHCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */ 211 #define GCLK_PCHCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */ 212 #define GCLK_PCHCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */ 213 #define GCLK_PCHCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */ 214 #define GCLK_PCHCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */ 215 #define GCLK_PCHCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */ 216 #define GCLK_PCHCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */ 217 #define GCLK_PCHCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */ 218 #define GCLK_PCHCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_PCHCTRL) Generic clock generator 8 */ 219 #define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos) 220 #define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos) 221 #define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos) 222 #define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos) 223 #define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos) 224 #define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos) 225 #define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos) 226 #define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos) 227 #define GCLK_PCHCTRL_GEN_GCLK8 (GCLK_PCHCTRL_GEN_GCLK8_Val << GCLK_PCHCTRL_GEN_Pos) 228 #define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */ 229 #define GCLK_PCHCTRL_CHEN (_U_(0x1) << GCLK_PCHCTRL_CHEN_Pos) 230 #define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */ 231 #define GCLK_PCHCTRL_WRTLOCK (_U_(0x1) << GCLK_PCHCTRL_WRTLOCK_Pos) 232 #define GCLK_PCHCTRL_MASK _U_(0x000000CF) /**< \brief (GCLK_PCHCTRL) MASK Register */ 233 234 /** \brief GCLK hardware registers */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef struct { 237 __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ 238 RoReg8 Reserved1[0x3]; 239 __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */ 240 RoReg8 Reserved2[0x18]; 241 __IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */ 242 RoReg8 Reserved3[0x3C]; 243 __IO GCLK_PCHCTRL_Type PCHCTRL[41]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */ 244 } Gclk; 245 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 246 247 /*@}*/ 248 249 #endif /* _SAMC21_GCLK_COMPONENT_ */ 250