1
2 /**
3 * \file
4 *
5 * \brief SAM 32k Oscillators Controller.
6 *
7 * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
8 *
9 * \asf_license_start
10 *
11 * \page License
12 *
13 * Subject to your compliance with these terms, you may use Microchip
14 * software and any derivatives exclusively with Microchip products.
15 * It is your responsibility to comply with third party license terms applicable
16 * to your use of third party software (including open source software) that
17 * may accompany Microchip software.
18 *
19 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
20 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
21 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
22 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
23 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
24 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
25 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
26 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
27 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
28 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
29 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
30 *
31 * \asf_license_stop
32 *
33 */
34 #include <hpl_init.h>
35 #include <hpl_osc32kctrl_config.h>
36
37 /**
38 * \brief Initialize 32 kHz clock sources
39 */
_osc32kctrl_init_sources(void)40 void _osc32kctrl_init_sources(void)
41 {
42 void * hw = (void *)OSC32KCTRL;
43 uint16_t calib = 0;
44
45 #if CONF_XOSC32K_CONFIG == 1
46 hri_osc32kctrl_write_XOSC32K_reg(
47 hw,
48 OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos)
49 | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos)
50 | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos)
51 | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) |
52 #ifdef CONF_XOSC32K_CGM
53 OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) |
54 #endif
55 (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos));
56
57 hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos));
58
59 hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos));
60 #endif
61
62 #if CONF_OSCULP32K_CONFIG == 1
63 calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw);
64 hri_osc32kctrl_write_OSCULP32K_reg(hw,
65 #if CONF_OSCULP32K_CALIB_ENABLE == 1
66 OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB)
67 #else
68 OSC32KCTRL_OSCULP32K_CALIB(calib)
69 #endif
70 );
71 #endif
72
73 #if CONF_XOSC32K_CONFIG
74 #if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0
75 while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw))
76 ;
77 #endif
78 #endif
79
80 hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL));
81 (void)calib;
82 }
83