1 /* Auto-generated config file hpl_gmac_config.h */ 2 #ifndef HPL_GMAC_CONFIG_H 3 #define HPL_GMAC_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 #include <peripheral_clk_config.h> 8 9 // <h> Network Control configuration 10 11 // <q> Enable LoopBack Local 12 // <i> Connects GTX to GRX, GTXEN to GRXDV and forces full duplex mode. 13 // <id> gmac_arch_ncr_lbl 14 #ifndef CONF_GMAC_NCR_LBL 15 #define CONF_GMAC_NCR_LBL 0 16 #endif 17 18 // <q> Management Port Enable 19 // <i> Enable the Management port 20 // <id> gmac_arch_ncr_mpe 21 #ifndef CONF_GMAC_NCR_MPE 22 #define CONF_GMAC_NCR_MPE 1 23 #endif 24 25 // <q> Enable write for Static Register 26 // <i> Make the statistics registers writable for functional test proposes. 27 // <id> gmac_arch_ncr_westat 28 #ifndef CONF_GMAC_NCR_WESTAT 29 #define CONF_GMAC_NCR_WESTAT 0 30 #endif 31 32 // <q> Enable Back pressure 33 // <i> If set in 10M or 100M half duplex mode, forces collisions on all received frames. 34 // <id> gmac_arch_ncr_bp 35 #ifndef CONF_GMAC_NCR_BP 36 #define CONF_GMAC_NCR_BP 0 37 #endif 38 39 // <q> Enable PFC Priority-based Pause Reception 40 // <i> Enables PFC negotiation and recognition of priority-based pause frames. 41 // <id> gmac_arch_ncr_enpbpr 42 #ifndef CONF_GMAC_NCR_ENPBPR 43 #define CONF_GMAC_NCR_ENPBPR 0 44 #endif 45 46 // <q> Enable PFC Priority-based Pause Frame 47 // <i> Takes the values stored in the Transmit PFC Pause Register. 48 // <id> gmac_arch_ncr_txpbpf 49 #ifndef CONF_GMAC_NCR_TXPBPF 50 #define CONF_GMAC_NCR_TXPBPF 0 51 #endif 52 53 // </h> 54 55 // <h> Network Configuration 56 57 // <q> 100Mbps Speed 58 // <i> Set to one to indicate 100 Mbps operation, zero for 10 Mbps. 59 // <id> gmac_arch_ncfgr_spd 60 #ifndef CONF_GMAC_NCFGR_SPD 61 #define CONF_GMAC_NCFGR_SPD 1 62 #endif 63 64 // <q> Enable Full Duplex 65 // <i> Enable Full duplex 66 // <id> gmac_arch_ncfgr_df 67 #ifndef CONF_GMAC_NCFGR_FD 68 #define CONF_GMAC_NCFGR_FD 1 69 #endif 70 71 // <q> Discard Non-VLAN Frames 72 // <i> Discard Non-VLAN Frames 73 // <id> gmac_arch_ncfgr_dnvlan 74 #ifndef CONF_GMAC_NCFGR_DNVLAN 75 #define CONF_GMAC_NCFGR_DNVLAN 0 76 #endif 77 78 // <q> Enable Jumbo Frame 79 // <i> Enable jumbo frames up to 10240 bytes to be accepted. 80 // <id> gmac_arch_ncfgr_jframe 81 #ifndef CONF_GMAC_NCFGR_JFRAME 82 #define CONF_GMAC_NCFGR_JFRAME 0 83 #endif 84 85 // <q> Copy All Frames 86 // <i> All valid frames will be accepted 87 // <id> gmac_arch_ncfgr_caf 88 #ifndef CONF_GMAC_NCFGR_CAF 89 #define CONF_GMAC_NCFGR_CAF 0 90 #endif 91 92 // <q> No broadcast 93 // <i> Frames addressed to the broadcast address of all ones will not be accepted. 94 // <id> gmac_arch_ncfgr_nbc 95 #ifndef CONF_GMAC_NCFGR_NBC 96 #define CONF_GMAC_NCFGR_NBC 0 97 #endif 98 99 // <q> Multicast Hash Enable 100 // <i> Multicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register. 101 // <id> gmac_arch_ncfgr_mtihen 102 #ifndef CONF_GMAC_NCFGR_MTIHEN 103 #define CONF_GMAC_NCFGR_MTIHEN 0 104 #endif 105 106 // <q> Unicast Hash Enable 107 // <i> Unicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register. 108 // <id> gmac_arch_ncfgr_unihen 109 #ifndef CONF_GMAC_NCFGR_UNIHEN 110 #define CONF_GMAC_NCFGR_UNIHEN 0 111 #endif 112 113 // <q> 1536 Maximum Frame Size 114 // <i> Accept frames up to 1536 bytes in length. 115 // <id> gmac_arch_ncfgr_maxfs 116 #ifndef CONF_GMAC_NCFGR_MAXFS 117 #define CONF_GMAC_NCFGR_MAXFS 1 118 #endif 119 120 // <q> Retry Test 121 // <i> Must be set to zero for normal operation. If set to one the backoff 122 // <i> between collisions will always be one slot time. Setting this bit to 123 // <i> one helps test the too many retries condition. Also used in the pause 124 // <i> frame tests to reduce the pause counter's decrement time from 512 bit 125 // <i> times, to every GRXCK cycle. 126 // <id> gmac_arch_ncfgr_rty 127 #ifndef CONF_GMAC_NCFGR_RTY 128 #define CONF_GMAC_NCFGR_RTY 0 129 #endif 130 131 // <q> Pause Enable 132 // <i> When set, transmission will pause if a non-zero 802.3 classic pause 133 // <i> frame is received and PFC has not been negotiated 134 // <id> gmac_arch_ncfgr_pen 135 #ifndef CONF_GMAC_NCFGR_PEN 136 #define CONF_GMAC_NCFGR_PEN 0 137 #endif 138 139 // <o> Receive Buffer Offset <0-3> 140 // <i> Indicates the number of bytes by which the received data is offset from 141 // <i> the start of the receive buffer. 142 // <id> gmac_arch_ncfgr_rxbufo 143 #ifndef CONF_GMAC_NCFGR_RXBUFO 144 #define CONF_GMAC_NCFGR_RXBUFO 0 145 #endif 146 147 // <q> Length Field Error Frame Discard 148 // <i> Setting this bit causes frames with a measured length shorter than the 149 // <i> extracted length field (as indicated by bytes 13 and 14 in a non-VLAN 150 // <i> tagged frame) to be discarded. This only applies to frames with a length 151 // <i> field less than 0x0600. 152 // <id> gmac_arch_ncfgr_lferd 153 #ifndef CONF_GMAC_NCFGR_LFERD 154 #define CONF_GMAC_NCFGR_LFERD 0 155 #endif 156 157 // <q> Remove FCS 158 // <i> Setting this bit will cause received frames to be written to memory 159 // <i> without their frame check sequence (last 4 bytes). The frame length 160 // <i> indicated will be reduced by four bytes in this mode. 161 // <id> gmac_arch_ncfgr_rfcs 162 #ifndef CONF_GMAC_NCFGR_RFCS 163 #define CONF_GMAC_NCFGR_RFCS 0 164 #endif 165 166 // <o> MDC Clock Division 167 // <i> Set according to MCK speed. These three bits determine the number MCK 168 // <i> will be divided by to generate Management Data Clock (MDC). For 169 // <i> conformance with the 802.3 specification, MDC must not exceed 2.5 MHz 170 // <i> (MDC is only active during MDIO read and write operations). 171 // <0=> 8 172 // <1=> 16 173 // <2=> 32 174 // <3=> 48 175 // <4=> 64 176 // <5=> 96 177 // <id> gmac_arch_ncfgr_clk 178 #ifndef CONF_GMAC_NCFGR_CLK 179 #define CONF_GMAC_NCFGR_CLK 4 180 #endif 181 182 /** 183 * For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz 184 **/ 185 #ifndef CONF_GMAC_MCK_FREQUENCY 186 #if CONF_GMAC_NCFGR_CLK == 0 187 #define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 8) 188 #elif CONF_GMAC_NCFGR_CLK == 1 189 #define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 16) 190 #elif CONF_GMAC_NCFGR_CLK == 2 191 #define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 32) 192 #elif CONF_GMAC_NCFGR_CLK == 3 193 #define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 48) 194 #elif CONF_GMAC_NCFGR_CLK == 4 195 #define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 64) 196 #elif CONF_GMAC_NCFGR_CLK == 5 197 #define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 96) 198 #endif 199 #endif 200 201 #if CONF_GMAC_MCK_FREQUENCY > 2500000 202 #warning For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz 203 #endif 204 // <q> Disable Copy of Pause Frames 205 // <i> Set to one to prevent valid pause frames being copied to memory. When 206 // <i> set, pause frames are not copied to memory regardless of the state of 207 // <i> the Copy All Frames bit, whether a hash match is found or whether a 208 // <i> type ID match is identified. If a destination address match is found, 209 // <i> the pause frame will be copied to memory. Note that valid pause frames 210 // <i> received will still increment pause statistics and pause the 211 // <i> transmission of frames as required. 212 // <id> gmac_arch_ncfgr_dcpf 213 #ifndef CONF_GMAC_NCFGR_DCPF 214 #define CONF_GMAC_NCFGR_DCPF 0 215 #endif 216 217 // <q> Receive Checksum Offload Enable 218 // <i> When set, the receive checksum engine is enabled. Frames with bad IP, 219 // <i> TCP or UDP checksums are discarded. 220 // <id> gmac_arch_ncfgr_rxcoen 221 #ifndef CONF_GMAC_NCFGR_RXCOEN 222 #define CONF_GMAC_NCFGR_RXCOEN 0 223 #endif 224 225 // <q> Enable Frames Received in Half Duplex 226 // <i> Enable frames to be received in half-duplex mode while transmittinga. 227 // <id> gmac_arch_ncfgr_efrhd 228 #ifndef CONF_GMAC_NCFGR_EFRHD 229 #define CONF_GMAC_NCFGR_EFRHD 0 230 #endif 231 232 // <q> Ignore RX FCS 233 // <i> When set, frames with FCS/CRC errors will not be rejected. FCS error 234 // <i> statistics will still be collected for frames with bad FCS and FCS 235 // <i> status will be recorded in frame's DMA descriptor. For normal operation 236 // <i> this bit must be set to zero. 237 // <id> gmac_arch_ncfgr_irxfcs 238 #ifndef CONF_GMAC_NCFGR_IRXFCS 239 #define CONF_GMAC_NCFGR_IRXFCS 0 240 #endif 241 242 // <q> IP Stretch Enable 243 // <i> When set, the transmit IPG can be increased above 96 bit times depending 244 // <i> on the previous frame length using the IPG Stretch Register. 245 // <id> gmac_arch_ncfgr_ipgsen 246 #ifndef CONF_GMAC_NCFGR_IPGSEN 247 #define CONF_GMAC_NCFGR_IPGSEN 0 248 #endif 249 250 // <q> Receive Bad Preamble 251 // <i> When set, frames with non-standard preamble are not rejected. 252 // <id> gmac_arch_ncfgr_rxbp 253 #ifndef CONF_GMAC_NCFGR_RXBP 254 #define CONF_GMAC_NCFGR_RXBP 0 255 #endif 256 257 // <q> Ignore IPG GRXER 258 // <i> When set, GRXER has no effect on the GMAC's operation when GRXDV is low. 259 // <id> gmac_arch_ncfgr_irxer 260 #ifndef CONF_GMAC_NCFGR_IRXER 261 #define CONF_GMAC_NCFGR_IRXER 0 262 #endif 263 264 // </h> 265 266 // <e> MII Configuration 267 // <id> gmac_arch_mii_cfg 268 269 // <o> MII Mode 270 // <i> Select MII or RMII mode 271 // <0=> RMII 272 // <1=> MII 273 // <id> gmac_arch_ur_mii 274 #ifndef CONF_GMAC_ur_mii 275 #define CONF_GMAC_UR_MII 0 276 #endif 277 278 // <o> PHY Clause Operation 279 // <i> Chose which Clause operation will be used 280 // <0=>Clause 45 Operation 281 // <1=>Clause 22 Operation 282 // <id> gmac_arch_cltto 283 #ifndef CONF_GMAC_CLTTO 284 #define CONF_GMAC_CLTTO 1 285 #endif 286 287 // </e> 288 289 // <e> Stacked VLAN Processing 290 // <i> When enabled, the first VLAN tag in a received frame will only be 291 // <i> accepted if the VLAN type field is equal to the User defined VLAN Type, 292 // <i> OR equal to the standard VLAN type (0x8100). Note that the second VLAN 293 // <i> tag of a Stacked VLAN packet will only be matched correctly if its 294 // <i> VLAN_TYPE field equals 0x8100. 295 // <id> gmac_arch_svlan_enable 296 #ifndef CONF_GMAC_SVLAN_ENABLE 297 #define CONF_GMAC_SVLAN_ENABLE 0 298 #endif 299 300 // <o> User Defined VLAN Type <0x0-0xFFFF> 301 // <i> User defined VLAN TYPE 302 // <id> gmac_arch_svlan_type 303 #ifndef CONF_GMAC_SVLAN_TYPE 304 #define CONF_GMAC_SVLAN_TYPE 0x8100 305 #endif 306 // </e> 307 308 // <e> DMA Configuration 309 // <i> The GMAC DMA controller is connected to the MAC FIFO interface and 310 // <i> provides a scatter-gather type capability for packet data storage. 311 // <i> The DMA implements packet buffering where dual-port memories are used 312 // <i> to buffer multiple frames. 313 // <id> gmac_arch_dma_cfg 314 #ifndef CONF_GMAC_DMA_CFG 315 #define CONF_GMAC_DMACFG 1 316 #endif 317 318 // <o> Fixed Burst Length for DMA Data Operations 319 // <i> Selects the burst length to attempt to use on the AHB when transferring 320 // <i> frame data. Not used for DMA management operations and only used where 321 // <i> space and data size allow. Otherwise SINGLE type AHB transfers are used. 322 // <1=> Always use SINGLE AHB bursts 323 // <4=> Always use INCR4 AHB bursts 324 // <8=> Always use INCR8 AHB bursts 325 // <16=> Always use INCR16 AHB bursts 326 // <id> gmac_arch_dcfgr_fbldo 327 #ifndef CONF_GMAC_DCFGR_FBLDO 328 #define CONF_GMAC_DCFGR_FBLDO 4 329 #endif 330 331 // <q> Endian Swap Mode Enable for Management Descriptor Accesses 332 // <i> When set, selects swapped endianism for AHB transfers. When clear, 333 // <i> selects little endian mode. 334 // <id> gmac_arch_dcfgr_esma 335 #ifndef CONF_GMAC_DCFGR_ESMA 336 #define CONF_GMAC_DCFGR_ESMA 0 337 #endif 338 339 // <q> Endian Swap Mode Enable for Packet Data Accesses 340 // <i> When set, selects swapped endianism for AHB transfers. When clear, 341 // <i> selects little endian mode. 342 // <id> gmac_arch_dcfgr_espa 343 #ifndef CONF_GMAC_DCFGR_ESPA 344 #define CONF_GMAC_DCFGR_ESPA 0 345 #endif 346 347 // <o> Receiver Packet Buffer Memory Size Select 348 // <i> Select the receive packet buffer size 349 // <0=> 0.5 Kbytes 350 // <1=> 1 Kbytes 351 // <2=> 2 Kbytes 352 // <3=> 4 Kbytes 353 // <id> gmac_arch_dcfgr_rxbms 354 #ifndef CONF_GMAC_DCFGR_RXBMS 355 #define CONF_GMAC_DCFGR_RXBMS 3 356 #endif 357 358 // <o> Transmitter Packet Buffer Memory Size Select 359 // <i> Select the Transmitter packet buffer size 360 // <0=> 2 Kbytes 361 // <1=> 4 Kbytes 362 // <id> gmac_arch_dcfgr_txpbms 363 #ifndef CONF_GMAC_DCFGR_TXPBMS 364 #define CONF_GMAC_DCFGR_TXPBMS 1 365 #endif 366 367 // <q> Transmitter Checksum Generation Offload Enable 368 // <i> Transmitter IP, TCP and UDP checksum generation offload enable. When 369 // <i> set, the transmitter checksum generation engine is enabled to calculate 370 // <i> and substitute checksums for transmit frames. When clear, frame data is 371 // <i> unaffected 372 // <id> gmac_arch_dcfgr_txcoen 373 #ifndef CONF_GMAC_DCFGR_TXCOEN 374 #define CONF_GMAC_DCFGR_TXCOEN 0 375 #endif 376 377 // <o> DMA Receive Buffer Size <1-255> 378 // <i> DMA receive buffer size in AHB system memory. The value defined by these 379 // <i> bits determines the size of buffer to use in main AHB system memory when 380 // <i> writing received data. The value is defined in multiples of 64 bytes, 381 // <i> thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02 382 // <i> corresponds to 128 bytes etc. 383 // <id> gmac_arch_dcfgr_drbs 384 #ifndef CONF_GMAC_DCFGR_DRBS 385 #define CONF_GMAC_DCFGR_DRBS 2 386 #endif 387 388 // <q> DMA Discard Received Packets 389 // <i> When set, the GMAC DMA will automatically discard receive packets from 390 // <i> the receiver packet buffer memory when no AHB resource is available. 391 // <i> When low, the received packets will remain to be stored in the SRAM 392 // <i> based packet buffer until AHB buffer resource next becomes available. 393 // <i> Note: packet buffer full store and forward mode should be enabled. 394 // <id> gmac_arch_dcfgr_ddrp 395 #ifndef CONF_GMAC_DCFGR_DDRP 396 #define CONF_GMAC_DCFGR_DDRP 0 397 #endif 398 // </e> 399 400 // <e> Advanced configuration 401 // <id> gmac_arch_adv_cfg 402 #ifndef CONF_GMAC_ADV_CFG 403 #define CONF_GMAC_ADV_CFG 1 404 #endif 405 406 // <o> Number of Transmit Buffer Descriptor <1-255> 407 // <i> Number of Transmit Buffer Descriptor 408 // <id> gmac_arch_txdescr_num 409 #ifndef CONF_GMAC_TXDESCR_NUM 410 #define CONF_GMAC_TXDESCR_NUM 2 411 #endif 412 413 // <o> Number of Receive Buffer Descriptor <1-255> 414 // <i> Number of Receive Buffer Descriptor 415 // <id> gmac_arch_rxdescr_num 416 #ifndef CONF_GMAC_RXDESCR_NUM 417 #define CONF_GMAC_RXDESCR_NUM 16 418 #endif 419 420 // <o> Byte size of Transmit Buffer <64-10240> 421 // <i> Byte size of buffer for each transmit buffer descriptor. 422 // <id> gmac_arch_txbuf_size 423 #ifndef CONF_GMAC_TXBUF_SIZE 424 #define CONF_GMAC_TXBUF_SIZE 1500 425 #endif 426 427 #ifndef CONF_GMAC_RXBUF_SIZE 428 #define CONF_GMAC_RXBUF_SIZE (CONF_GMAC_DCFGR_DRBS * 64) 429 #endif 430 431 // <e> Enable Transmit Partial Store and Forward 432 // <i> This allows for a reduced latency but there are performance implications. 433 // <id> gmac_arch_tpsf_en 434 #ifndef CONF_GMAC_TPSF_EN 435 #define CONF_GMAC_TPSF_EN 0 436 #endif 437 438 // <o> Watermark <20-4095> 439 // <i> Byte size of buffer for each transmit buffer descriptor. 440 // <id> gmac_arch_tpsf_wm 441 #ifndef CONF_GMAC_TPSF_WM 442 #define CONF_GMAC_TPSF_WM 100 443 #endif 444 // </e> 445 446 // <e> Enable Receive Partial Store and Forward 447 // <i> This allows for a reduced latency but there are performance implications. 448 // <id> gmac_arch_rpsf_en 449 #ifndef CONF_GMAC_RPSF_EN 450 #define CONF_GMAC_RPSF_EN 0 451 #endif 452 453 // <o> Watermark <20-4095> 454 // <i> Byte size of buffer for each transmite buffer descriptor. 455 // <id> gmac_arch_rpsf_wm 456 #ifndef CONF_GMAC_RPSF_WM 457 #define CONF_GMAC_RPSF_WM 100 458 #endif 459 460 // <o> IPG Stretch Multiple <0-15> 461 // <i> This value will multiplied with the previously transmitted frame length 462 // <i> (including preamble) 463 // <id> gmac_arch_ipgs_fl_mul 464 #ifndef CONF_GMAC_IPGS_FL_MUL 465 #define CONF_GMAC_IPGS_FL_MUL 1 466 #endif 467 468 // <o> IPG Stretch Divide <1-16> 469 // <i> Divide the frame length. If the resulting number is greater than 96 and 470 // <i> IP Stretch Enabled then the resulting number is used for the transmit 471 // <i> inter-packet-gap 472 // <id> gmac_arch_ipgs_fl_div 473 #ifndef CONF_GMAC_IPGS_FL_DIV 474 #define CONF_GMAC_IPGS_FL_DIV 1 475 #endif 476 477 // </e> 478 479 // </e> 480 481 // <<< end of configuration section >>> 482 483 #endif // HPL_GMAC_CONFIG_H 484