1 /* Auto-generated config file hpl_sercom_config.h */ 2 #ifndef HPL_SERCOM_CONFIG_H 3 #define HPL_SERCOM_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 #include <peripheral_clk_config.h> 8 9 #ifndef CONF_SERCOM_2_USART_ENABLE 10 #define CONF_SERCOM_2_USART_ENABLE 1 11 #endif 12 13 // <h> Basic Configuration 14 15 // <q> Receive buffer enable 16 // <i> Enable input buffer in SERCOM module 17 // <id> usart_rx_enable 18 #ifndef CONF_SERCOM_2_USART_RXEN 19 #define CONF_SERCOM_2_USART_RXEN 1 20 #endif 21 22 // <q> Transmitt buffer enable 23 // <i> Enable output buffer in SERCOM module 24 // <id> usart_tx_enable 25 #ifndef CONF_SERCOM_2_USART_TXEN 26 #define CONF_SERCOM_2_USART_TXEN 1 27 #endif 28 29 // <o> Frame parity 30 // <0x0=>No parity 31 // <0x1=>Even parity 32 // <0x2=>Odd parity 33 // <i> Parity bit mode for USART frame 34 // <id> usart_parity 35 #ifndef CONF_SERCOM_2_USART_PARITY 36 #define CONF_SERCOM_2_USART_PARITY 0x0 37 #endif 38 39 // <o> Character Size 40 // <0x0=>8 bits 41 // <0x1=>9 bits 42 // <0x5=>5 bits 43 // <0x6=>6 bits 44 // <0x7=>7 bits 45 // <i> Data character size in USART frame 46 // <id> usart_character_size 47 #ifndef CONF_SERCOM_2_USART_CHSIZE 48 #define CONF_SERCOM_2_USART_CHSIZE 0x0 49 #endif 50 51 // <o> Stop Bit 52 // <0=>One stop bit 53 // <1=>Two stop bits 54 // <i> Number of stop bits in USART frame 55 // <id> usart_stop_bit 56 #ifndef CONF_SERCOM_2_USART_SBMODE 57 #define CONF_SERCOM_2_USART_SBMODE 0 58 #endif 59 60 // <o> Baud rate <1-6250000> 61 // <i> USART baud rate setting 62 // <id> usart_baud_rate 63 #ifndef CONF_SERCOM_2_USART_BAUD 64 #define CONF_SERCOM_2_USART_BAUD 115200 65 #endif 66 67 // </h> 68 69 // <e> Advanced configuration 70 // <id> usart_advanced 71 #ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG 72 #define CONF_SERCOM_2_USART_ADVANCED_CONFIG 1 73 #endif 74 75 // <q> Run in stand-by 76 // <i> Keep the module running in standby sleep mode 77 // <id> usart_arch_runstdby 78 #ifndef CONF_SERCOM_2_USART_RUNSTDBY 79 #define CONF_SERCOM_2_USART_RUNSTDBY 0 80 #endif 81 82 // <q> Immediate Buffer Overflow Notification 83 // <i> Controls when the BUFOVF status bit is asserted 84 // <id> usart_arch_ibon 85 #ifndef CONF_SERCOM_2_USART_IBON 86 #define CONF_SERCOM_2_USART_IBON 0 87 #endif 88 89 // <q> Start of Frame Detection Enable 90 // <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) 91 // <id> usart_arch_sfde 92 #ifndef CONF_SERCOM_2_USART_SFDE 93 #define CONF_SERCOM_2_USART_SFDE 0 94 #endif 95 96 // <q> Collision Detection Enable 97 // <i> Collision detection enable 98 // <id> usart_arch_cloden 99 #ifndef CONF_SERCOM_2_USART_CLODEN 100 #define CONF_SERCOM_2_USART_CLODEN 0 101 #endif 102 103 // <o> Operating Mode 104 // <0x0=>USART with external clock 105 // <0x1=>USART with internal clock 106 // <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. 107 // <id> usart_arch_clock_mode 108 #ifndef CONF_SERCOM_2_USART_MODE 109 #define CONF_SERCOM_2_USART_MODE 0x1 110 #endif 111 112 // <o> Sample Rate 113 // <0x0=>16x arithmetic 114 // <0x1=>16x fractional 115 // <0x2=>8x arithmetic 116 // <0x3=>8x fractional 117 // <0x4=>3x arithmetic 118 // <i> How many over-sampling bits used when sampling data state 119 // <id> usart_arch_sampr 120 #ifndef CONF_SERCOM_2_USART_SAMPR 121 #define CONF_SERCOM_2_USART_SAMPR 0x0 122 #endif 123 124 // <o> Sample Adjustment 125 // <0x0=>7-8-9 (3-4-5 8-bit over-sampling) 126 // <0x1=>9-10-11 (4-5-6 8-bit over-sampling) 127 // <0x2=>11-12-13 (5-6-7 8-bit over-sampling) 128 // <0x3=>13-14-15 (6-7-8 8-bit over-sampling) 129 // <i> Adjust which samples to use for data sampling in asynchronous mode 130 // <id> usart_arch_sampa 131 #ifndef CONF_SERCOM_2_USART_SAMPA 132 #define CONF_SERCOM_2_USART_SAMPA 0x0 133 #endif 134 135 // <o> Fractional Part <0-7> 136 // <i> Fractional part of the baud rate if baud rate generator is in fractional mode 137 // <id> usart_arch_fractional 138 #ifndef CONF_SERCOM_2_USART_FRACTIONAL 139 #define CONF_SERCOM_2_USART_FRACTIONAL 0x0 140 #endif 141 142 // <o> Data Order 143 // <0=>MSB is transmitted first 144 // <1=>LSB is transmitted first 145 // <i> Data order of the data bits in the frame 146 // <id> usart_arch_dord 147 #ifndef CONF_SERCOM_2_USART_DORD 148 #define CONF_SERCOM_2_USART_DORD 1 149 #endif 150 151 // Does not do anything in UART mode 152 #define CONF_SERCOM_2_USART_CPOL 0 153 154 // <o> Encoding Format 155 // <0=>No encoding 156 // <1=>IrDA encoded 157 // <id> usart_arch_enc 158 #ifndef CONF_SERCOM_2_USART_ENC 159 #define CONF_SERCOM_2_USART_ENC 0 160 #endif 161 162 // <o> LIN Slave Enable 163 // <i> Break Character Detection and Auto-Baud/LIN Slave Enable. 164 // <i> Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). 165 // <0=>Disable 166 // <1=>Enable 167 // <id> usart_arch_lin_slave_enable 168 #ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 169 #define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 170 #endif 171 172 // <o> Debug Stop Mode 173 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger. 174 // <0=>Keep running 175 // <1=>Halt 176 // <id> usart_arch_dbgstop 177 #ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE 178 #define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 179 #endif 180 181 // </e> 182 183 #ifndef CONF_SERCOM_2_USART_INACK 184 #define CONF_SERCOM_2_USART_INACK 0x0 185 #endif 186 187 #ifndef CONF_SERCOM_2_USART_DSNACK 188 #define CONF_SERCOM_2_USART_DSNACK 0x0 189 #endif 190 191 #ifndef CONF_SERCOM_2_USART_MAXITER 192 #define CONF_SERCOM_2_USART_MAXITER 0x7 193 #endif 194 195 #ifndef CONF_SERCOM_2_USART_GTIME 196 #define CONF_SERCOM_2_USART_GTIME 0x2 197 #endif 198 199 #define CONF_SERCOM_2_USART_RXINV 0x0 200 #define CONF_SERCOM_2_USART_TXINV 0x0 201 202 #ifndef CONF_SERCOM_2_USART_CMODE 203 #define CONF_SERCOM_2_USART_CMODE 0 204 #endif 205 206 #ifndef CONF_SERCOM_2_USART_RXPO 207 #define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */ 208 #endif 209 210 #ifndef CONF_SERCOM_2_USART_TXPO 211 #define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */ 212 #endif 213 214 /* Set correct parity settings in register interface based on PARITY setting */ 215 #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 216 #if CONF_SERCOM_2_USART_PARITY == 0 217 #define CONF_SERCOM_2_USART_PMODE 0 218 #define CONF_SERCOM_2_USART_FORM 4 219 #else 220 #define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 221 #define CONF_SERCOM_2_USART_FORM 5 222 #endif 223 #else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ 224 #if CONF_SERCOM_2_USART_PARITY == 0 225 #define CONF_SERCOM_2_USART_PMODE 0 226 #define CONF_SERCOM_2_USART_FORM 0 227 #else 228 #define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 229 #define CONF_SERCOM_2_USART_FORM 1 230 #endif 231 #endif 232 233 // Calculate BAUD register value in UART mode 234 #if CONF_SERCOM_2_USART_SAMPR == 0 235 #ifndef CONF_SERCOM_2_USART_BAUD_RATE 236 #define CONF_SERCOM_2_USART_BAUD_RATE \ 237 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) 238 #endif 239 #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 240 #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 241 #endif 242 #elif CONF_SERCOM_2_USART_SAMPR == 1 243 #ifndef CONF_SERCOM_2_USART_BAUD_RATE 244 #define CONF_SERCOM_2_USART_BAUD_RATE \ 245 ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) 246 #endif 247 #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 248 #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 249 #endif 250 #elif CONF_SERCOM_2_USART_SAMPR == 2 251 #ifndef CONF_SERCOM_2_USART_BAUD_RATE 252 #define CONF_SERCOM_2_USART_BAUD_RATE \ 253 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) 254 #endif 255 #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 256 #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 257 #endif 258 #elif CONF_SERCOM_2_USART_SAMPR == 3 259 #ifndef CONF_SERCOM_2_USART_BAUD_RATE 260 #define CONF_SERCOM_2_USART_BAUD_RATE \ 261 ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) 262 #endif 263 #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 264 #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 265 #endif 266 #elif CONF_SERCOM_2_USART_SAMPR == 4 267 #ifndef CONF_SERCOM_2_USART_BAUD_RATE 268 #define CONF_SERCOM_2_USART_BAUD_RATE \ 269 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) 270 #endif 271 #ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 272 #define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 273 #endif 274 #endif 275 276 #include <peripheral_clk_config.h> 277 278 #ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER 279 #define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) 280 #endif 281 282 #ifndef CONF_SERCOM_7_I2CM_ENABLE 283 #define CONF_SERCOM_7_I2CM_ENABLE 1 284 #endif 285 286 // <h> Basic 287 288 // <o> I2C Bus clock speed (Hz) <1-400000> 289 // <i> I2C Bus clock (SCL) speed measured in Hz 290 // <id> i2c_master_baud_rate 291 #ifndef CONF_SERCOM_7_I2CM_BAUD 292 #define CONF_SERCOM_7_I2CM_BAUD 100000 293 #endif 294 295 // </h> 296 297 // <e> Advanced 298 // <id> i2c_master_advanced 299 #ifndef CONF_SERCOM_7_I2CM_ADVANCED_CONFIG 300 #define CONF_SERCOM_7_I2CM_ADVANCED_CONFIG 1 301 #endif 302 303 // <o> TRise (ns) <0-300> 304 // <i> Determined by the bus impedance, check electric characteristics in the datasheet 305 // <i> Standard Fast Mode: typical 215ns, max 300ns 306 // <i> Fast Mode +: typical 60ns, max 100ns 307 // <i> High Speed Mode: typical 20ns, max 40ns 308 // <id> i2c_master_arch_trise 309 310 #ifndef CONF_SERCOM_7_I2CM_TRISE 311 #define CONF_SERCOM_7_I2CM_TRISE 215 312 #endif 313 314 // <q> Master SCL Low Extended Time-Out (MEXTTOEN) 315 // <i> This enables the master SCL low extend time-out 316 // <id> i2c_master_arch_mexttoen 317 #ifndef CONF_SERCOM_7_I2CM_MEXTTOEN 318 #define CONF_SERCOM_7_I2CM_MEXTTOEN 1 319 #endif 320 321 // <q> Slave SCL Low Extend Time-Out (SEXTTOEN) 322 // <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine 323 // <id> i2c_master_arch_sexttoen 324 #ifndef CONF_SERCOM_7_I2CM_SEXTTOEN 325 #define CONF_SERCOM_7_I2CM_SEXTTOEN 0 326 #endif 327 328 // <q> SCL Low Time-Out (LOWTOUT) 329 // <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold 330 // <id> i2c_master_arch_lowtout 331 #ifndef CONF_SERCOM_7_I2CM_LOWTOUT 332 #define CONF_SERCOM_7_I2CM_LOWTOUT 1 333 #endif 334 335 // <o> Inactive Time-Out (INACTOUT) 336 // <0x0=>Disabled 337 // <0x1=>5-6 SCL cycle time-out(50-60us) 338 // <0x2=>10-11 SCL cycle time-out(100-110us) 339 // <0x3=>20-21 SCL cycle time-out(200-210us) 340 // <i> Defines if inactivity time-out should be enabled, and how long the time-out should be 341 // <id> i2c_master_arch_inactout 342 #ifndef CONF_SERCOM_7_I2CM_INACTOUT 343 #define CONF_SERCOM_7_I2CM_INACTOUT 0x3 344 #endif 345 346 // <o> SDA Hold Time (SDAHOLD) 347 // <0=>Disabled 348 // <1=>50-100ns hold time 349 // <2=>300-600ns hold time 350 // <3=>400-800ns hold time 351 // <i> Defines the SDA hold time with respect to the negative edge of SCL 352 // <id> i2c_master_arch_sdahold 353 #ifndef CONF_SERCOM_7_I2CM_SDAHOLD 354 #define CONF_SERCOM_7_I2CM_SDAHOLD 0x2 355 #endif 356 357 // <q> Run in stand-by 358 // <i> Determine if the module shall run in standby sleep mode 359 // <id> i2c_master_arch_runstdby 360 #ifndef CONF_SERCOM_7_I2CM_RUNSTDBY 361 #define CONF_SERCOM_7_I2CM_RUNSTDBY 0 362 #endif 363 364 // <o> Debug Stop Mode 365 // <i> Behavior of the baud-rate generator when CPU is halted by external debugger. 366 // <0=>Keep running 367 // <1=>Halt 368 // <id> i2c_master_arch_dbgstop 369 #ifndef CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE 370 #define CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE 0 371 #endif 372 373 // </e> 374 375 #ifndef CONF_SERCOM_7_I2CM_SPEED 376 #define CONF_SERCOM_7_I2CM_SPEED 0x00 // Speed: Standard/Fast mode 377 #endif 378 #if CONF_SERCOM_7_I2CM_TRISE < 215 || CONF_SERCOM_7_I2CM_TRISE > 300 379 #warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns 380 #undef CONF_SERCOM_7_I2CM_TRISE 381 #define CONF_SERCOM_7_I2CM_TRISE 215U 382 #endif 383 384 // gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) 385 // BAUD + BAUDLOW = -------------------------------------------------------------------- 386 // i2c_scl_freq 387 // BAUD: register value low [7:0] 388 // BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW 389 #define CONF_SERCOM_7_I2CM_BAUD_BAUDLOW \ 390 (((CONF_GCLK_SERCOM7_CORE_FREQUENCY - (CONF_SERCOM_7_I2CM_BAUD * 10U) \ 391 - (CONF_SERCOM_7_I2CM_TRISE * (CONF_SERCOM_7_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM7_CORE_FREQUENCY / 10000U) \ 392 / 1000U)) \ 393 * 10U \ 394 + 5U) \ 395 / (CONF_SERCOM_7_I2CM_BAUD * 10U)) 396 #ifndef CONF_SERCOM_7_I2CM_BAUD_RATE 397 #if CONF_SERCOM_7_I2CM_BAUD_BAUDLOW > (0xFF * 2) 398 #warning Requested I2C baudrate too low, please check 399 #define CONF_SERCOM_7_I2CM_BAUD_RATE 0xFF 400 #elif CONF_SERCOM_7_I2CM_BAUD_BAUDLOW <= 1 401 #warning Requested I2C baudrate too high, please check 402 #define CONF_SERCOM_7_I2CM_BAUD_RATE 1 403 #else 404 #define CONF_SERCOM_7_I2CM_BAUD_RATE \ 405 ((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW & 0x1) \ 406 ? (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ 407 : (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2)) 408 #endif 409 #endif 410 411 // <<< end of configuration section >>> 412 413 #endif // HPL_SERCOM_CONFIG_H 414