1 /** 2 * \file 3 * 4 * \brief SPI Slave Async related functionality declaration. 5 * 6 * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Subject to your compliance with these terms, you may use Microchip 13 * software and any derivatives exclusively with Microchip products. 14 * It is your responsibility to comply with third party license terms applicable 15 * to your use of third party software (including open source software) that 16 * may accompany Microchip software. 17 * 18 * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, 19 * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, 20 * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, 21 * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE 22 * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL 23 * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE 24 * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 25 * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT 26 * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY 27 * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, 28 * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. 29 * 30 * \asf_license_stop 31 * 32 */ 33 34 #ifndef _HPL_SPI_S_ASYNC_H_INCLUDED 35 #define _HPL_SPI_S_ASYNC_H_INCLUDED 36 37 #include <hpl_spi_async.h> 38 39 /** 40 * \addtogroup hpl_spi HPL SPI 41 * 42 * 43 *@{ 44 */ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 /** Uses common SPI async device driver. */ 51 #define _spi_s_async_dev _spi_async_dev 52 53 #define _spi_s_async_dev_cb_type _spi_async_dev_cb_type 54 55 /** Uses common SPI async device driver complete callback type. */ 56 #define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t 57 58 /** Uses common SPI async device driver transfer callback type. */ 59 #define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t 60 61 /** 62 * \name HPL functions 63 */ 64 //@{ 65 /** 66 * \brief Initialize SPI for access with interrupts 67 * It will load default hardware configuration and software struct. 68 * \param[in, out] dev Pointer to the SPI device instance. 69 * \param[in] hw Pointer to the hardware base. 70 * \return Operation status. 71 * \retval ERR_INVALID_ARG Input parameter problem. 72 * \retval ERR_BUSY SPI hardware not ready (resetting). 73 * \retval ERR_DENIED SPI has been enabled. 74 * \retval 0 Operation done successfully. 75 */ 76 int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); 77 78 /** 79 * \brief Initialize SPI for access with interrupts 80 * Disable, reset the hardware and the software struct. 81 * \param[in, out] dev Pointer to the SPI device instance. 82 * \return Operation status. 83 * \retval 0 Operation done successfully. 84 */ 85 int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); 86 87 /** 88 * \brief Enable SPI for access with interrupts 89 * Enable the SPI and enable callback generation of receive and error 90 * interrupts. 91 * \param[in, out] dev Pointer to the SPI device instance. 92 * \return Operation status. 93 * \retval ERR_INVALID_ARG Input parameter problem. 94 * \retval ERR_BUSY SPI hardware not ready (resetting). 95 * \retval 0 Operation done successfully. 96 */ 97 int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); 98 99 /** 100 * \brief Disable SPI for access without interrupts 101 * Disable SPI and interrupts. Deactivate all CS pins if works as master. 102 * \param[in, out] dev Pointer to the SPI device instance. 103 * \return Operation status. 104 * \retval 0 Operation done successfully. 105 */ 106 int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); 107 108 /** 109 * \brief Set SPI transfer mode 110 * Set SPI transfer mode (\ref spi_transfer_mode), 111 * which controls clock polarity and clock phase. 112 * Mode 0: leading edge is rising edge, data sample on leading edge. 113 * Mode 1: leading edge is rising edge, data sample on trailing edge. 114 * Mode 2: leading edge is falling edge, data sample on leading edge. 115 * Mode 3: leading edge is falling edge, data sample on trailing edge. 116 * \param[in, out] dev Pointer to the SPI device instance. 117 * \param[in] mode The SPI transfer mode. 118 * \return Operation status. 119 * \retval ERR_BUSY SPI is not ready to accept new setting. 120 * \retval 0 Operation done successfully. 121 */ 122 int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); 123 124 /** 125 * \brief Set SPI baudrate 126 * \param[in, out] dev Pointer to the SPI device instance. 127 * \param[in] char_size The character size, see \ref spi_char_size. 128 * \return Operation status. 129 * \retval ERR_INVALID_ARG The character size is not supported. 130 * \retval ERR_BUSY SPI is not ready to accept new setting. 131 * \retval 0 Operation done successfully. 132 */ 133 int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); 134 135 /** 136 * \brief Set SPI data order 137 * \param[in, out] dev Pointer to the SPI device instance. 138 * \param[in] dord SPI data order (LSB/MSB first). 139 * \return Operation status. 140 * \retval ERR_INVALID_ARG The character size is not supported. 141 * \retval ERR_BUSY SPI is not ready to accept new setting. 142 * \retval 0 Operation done successfully. 143 */ 144 int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); 145 146 /** 147 * \brief Enable interrupt on character output 148 * 149 * Enable interrupt when a new character can be written 150 * to the SPI device. 151 * 152 * \param[in] dev Pointer to the SPI device instance 153 * \param[in] state true = enable output interrupt 154 * false = disable output interrupt 155 * 156 * \return Status code 157 * \retval 0 Ok status 158 */ 159 int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); 160 161 /** 162 * \brief Enable interrupt on character input 163 * 164 * Enable interrupt when a new character is ready to be 165 * read from the SPI device. 166 * 167 * \param[in] dev Pointer to the SPI device instance 168 * \param[in] state true = enable input interrupts 169 * false = disable input interrupt 170 * 171 * \return Status code 172 * \retvat 0 OK Status 173 */ 174 int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); 175 176 /** 177 * \brief Enable interrupt on Slave Select (SS) rising 178 * 179 * \param[in] dev Pointer to the SPI device instance 180 * \param[in] state true = enable input interrupts 181 * false = disable input interrupt 182 * 183 * \return Status code 184 * \retvat 0 OK Status 185 */ 186 int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); 187 188 /** 189 * \brief Read one character to SPI device instance 190 * \param[in, out] dev Pointer to the SPI device instance. 191 * 192 * \return Character read from SPI module 193 */ 194 uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); 195 196 /** 197 * \brief Write one character to assigned buffer 198 * \param[in, out] dev Pointer to the SPI device instance. 199 * \param[in] data 200 * 201 * \return Status code of write operation 202 * \retval 0 Write operation OK 203 */ 204 int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); 205 206 /** 207 * \brief Register the SPI device callback 208 * \param[in, out] dev Pointer to the SPI device instance. 209 * \param[in] cb_type The callback type. 210 * \param[in] func The callback function to register. NULL to disable callback. 211 * \return Always 0. 212 */ 213 int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, 214 const FUNC_PTR func); 215 216 /** 217 * \brief Enable/disable SPI slave interrupt 218 * 219 * param[in] device The pointer to SPI slave device instance 220 * param[in] type The type of interrupt to disable/enable if applicable 221 * param[in] state Enable or disable 222 */ 223 void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, 224 const bool state); 225 //@} 226 227 #ifdef __cplusplus 228 } 229 #endif 230 231 /**@}*/ 232 #endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ 233