README.md
1# SAML10E16A BSP Introduction
2
3[中文](README_zh.md)
4- MCU: ATSAML10E16A @32MHz, 64KB FLASH, 16KB RAM, 1.62V – 3.63V
5- L10: Cortex-M23 + Hardware multiplier & divider + ultra low power(< 25 μA/MHz)
6- Pin: E=32 pins, D=24pins
7- Flash: 16=64KB, 15=32KB, 14=16KB(size=2^n)
8- SRAM : 16KB(Flash 64KB), 8KB(Flash 32KB), 4KB(Flash 16KB)
9- Datasheet: <https://www.microchip.com/en-us/product/ATSAML10E16A>
10
11#### KEY FEATURES
12
13#### Core
14 - 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm® Cortex®-M23 with:
15 - Single-cycle hardware multiplier
16 - Hardware divider
17 - Nested Vector Interrupt Controller (NVIC)
18 - Memory Protection Unit (MPU)
19 - Stack Limit Checking
20 - TrustZone® for ARMv8-M (optional)
21
22#### Memories
23 - 16/32/64-KB Flash
24 - 4/8/16-KB SRAM
25 - 2-KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
26 - 256 bytes TrustRAM with physical protection features
27
28#### System
29 - Power-on Reset (POR) and programmable Brown-out Detection (BOD)
30 - 8-channel Direct Memory Access Controller (DMAC)
31 - 8-channel event system for Inter-peripheral Core-independent Operation
32 - CRC-32 generator
33
34#### Clock Management
35 - Flexible clock distribution optimized for low power
36 - 32.768 kHz crystal oscillator
37 - 32.768 kHz ultra low-power internal RC oscillator
38 - 0.4 to 32 MHz crystal oscillator
39 - 16/12/8/4 MHz low-power internal RC oscillator
40 - Ultra low-power digital Frequency-Locked Loop (DFLLULP)
41 - 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
42 - One frequency meter
43 - Low-Power and Power Management
44 - Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
45 - Active mode (< 25 μA/MHz)
46 - Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time
47 - Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time
48 - Off mode (< 100 nA)
49 - Static and dynamic power gating architecture
50 - Sleepwalking peripherals
51 - Two performance levels
52 - Embedded Buck/LDO regulator with on-the-fly selection
53
54#### Security
55 - Up to four tamper pins for static and dynamic intrusion detections
56 - Data Flash
57 - Optimized for secure storage
58 - Address and data scrambling with user-defined key (optional)
59 - Rapid tamper erase on scrambling key and on one user-defined row
60 - Silent access for data read noise reduction
61 - TrustRAM
62 - Address and data scrambling with user-defined key
63 - Chip-level tamper detection on physical RAM to resist microprobing attacks
64 - Rapid tamper erase on scrambling key and RAM data
65 - Silent access for data read noise reduction
66 - Data remanence prevention
67 - Peripherals
68 - One True Random Generator (TRNG)
69 - AES-128, SHA-256, and GCM cryptography accelerators (optional)
70 - Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional)
71 - TrustZone for flexible hardware isolation of memories and peripherals (optional)
72 - Up to six regions for the Flash
73 - Up to two regions for the Data Flash
74 - Up to two regions for the SRAM
75 - Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel
76 - Secure Boot with SHA-based authentication (optional)
77 - Up to three debug access levels
78 - Up to three Chip Erase commands to erase part of or the entire embedded memories
79 - Unique 128-bit serial number
80 - SAM L11 Securely Key Provisioned (KPH) (optional)
81 - Key Provisioning using Root of Trust flow
82 - Security Software Framework using Kinibi-M™ Software Development Kit (SDK)
83
84#### Advanced Analog and Touch
85 - One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
86 - Two Analog Comparators (AC) with window compare function
87 - One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs
88 - Three Operational Amplifiers (OPAMP)
89 - One enhanced Peripheral Touch Controller (PTC):
90 - Up to 20 self-capacitance channels
91 - Up to 100 (10x10) mutual-capacitance channels
92 - Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
93 - Hardware noise filtering and noise signal desynchronization for high conducted immunity
94 - Driven Shield Plus for better noise immunity and moisture tolerance
95 - Parallel Acquisition through Polarity control
96 - Supports wake-up on touch from Standby Sleep mode
97
98#### Communication Interfaces
99 - Up to three Serial Communication Interfaces (SERCOM) that can operate as:
100 - USART with full-duplex and single-wire half-duplex configuration
101 - I2C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the second instance
102 - Serial Peripheral Interface (SPI)
103 - ISO7816 on one instance (Available on 32-pin packages only)
104 - RS-485 on one instance (Available on 32-pin packages only)
105 - LIN Slave on one instance (Available on 32-pin packages only)
106 - Timers/Output Compare/Input Capture
107 - Three 16-bit Timers/Counters (TC), each configurable as:
108 - One 16-bit TC with two compare/capture channels
109 - One 8-bit TC with two compare/capture channels
110 - One 32-bit TC with two compare/capture channels, by using two TCs
111 - 32-bit Real-Time Counter (RTC) with clock/calendar functions
112 - Watchdog Timer (WDT) with Window mode
113 - Input/Output (I/O)
114 - Up to 25 programmable I/O lines
115 - Eight external interrupts (EIC)
116 - One non-maskable interrupt (NMI)
117 - One Configurable Custom Logic (CCL) that supports:
118 - Combinatorial logic functions, such as AND, NAND, OR, and NOR
119 - Sequential logic functions, such as Flip-Flop and Latches
120
121#### Qualification
122 - AEC-Q100 Grade 1 (-40°C to 125°C)
123 - Class-B safety library, IEC 60730 (future)
124
125#### Packages
126 - 24-pin VQFN(4*4mm/17 I/O pins)
127 - 32-pin VQFN(5*5mm/25 I/O pins)
128 - 32-pin TQFP(7*7mm/17 I/O pins)
129 - 32-pin WLCSP(2.79*2.79mm/25 I/O pins)
130
131#### Board info
132- [SAM L10 XPLAINED PRO](https://ww1.microchip.com/downloads/en/Appnotes/Getting-Started-with-SAM%20L10L11-Xplained-Pro-DS00002722A.pdf)
133
README_zh.md
1# SAML10E16A BSP 介绍
2
3[English](README.md)
4- MCU: ATSAML10E16A @32MHz, 64KB FLASH, 16KB RAM, 1.62V – 3.63V
5- L10: Cortex-M23内核 + 硬件乘除法 + 超低功耗(< 25 μA/MHz)
6- 管脚: E=32 pins, D=24pins
7- Flash: 16=64KB, 15=32KB, 14=16KB(size=2^n)
8- SRAM : 16KB(Flash 64KB), 8KB(Flash 32KB), 4KB(Flash 16KB)
9- 手册: <https://www.microchip.com/en-us/product/ATSAML10E16A>
10
11#### 关键特性
12
13#### 内核
14 - 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS) Arm® Cortex®-M23 with:
15 - Single-cycle hardware multiplier
16 - Hardware divider
17 - Nested Vector Interrupt Controller (NVIC)
18 - Memory Protection Unit (MPU)
19 - Stack Limit Checking
20 - TrustZone® for ARMv8-M (optional)
21
22#### 内存
23 - 16/32/64-KB Flash
24 - 4/8/16-KB SRAM
25 - 2-KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
26 - 256 bytes TrustRAM with physical protection features
27
28#### 系统特性
29 - Power-on Reset (POR) and programmable Brown-out Detection (BOD)
30 - 8-channel Direct Memory Access Controller (DMAC)
31 - 8-channel event system for Inter-peripheral Core-independent Operation
32 - CRC-32 generator
33
34#### 时钟系统
35 - Flexible clock distribution optimized for low power
36 - 32.768 kHz crystal oscillator
37 - 32.768 kHz ultra low-power internal RC oscillator
38 - 0.4 to 32 MHz crystal oscillator
39 - 16/12/8/4 MHz low-power internal RC oscillator
40 - Ultra low-power digital Frequency-Locked Loop (DFLLULP)
41 - 32-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)
42 - One frequency meter
43 - Low-Power and Power Management
44 - Active, Idle, Standby with partial or full SRAM retention and off sleep modes:
45 - Active mode (< 25 μA/MHz)
46 - Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time
47 - Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time
48 - Off mode (< 100 nA)
49 - Static and dynamic power gating architecture
50 - Sleepwalking peripherals
51 - Two performance levels
52 - Embedded Buck/LDO regulator with on-the-fly selection
53
54#### 安全特性
55 - Up to four tamper pins for static and dynamic intrusion detections
56 - Data Flash
57 - Optimized for secure storage
58 - Address and data scrambling with user-defined key (optional)
59 - Rapid tamper erase on scrambling key and on one user-defined row
60 - Silent access for data read noise reduction
61 - TrustRAM
62 - Address and data scrambling with user-defined key
63 - Chip-level tamper detection on physical RAM to resist microprobing attacks
64 - Rapid tamper erase on scrambling key and RAM data
65 - Silent access for data read noise reduction
66 - Data remanence prevention
67 - Peripherals
68 - One True Random Generator (TRNG)
69 - AES-128, SHA-256, and GCM cryptography accelerators (optional)
70 - Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional)
71 - TrustZone for flexible hardware isolation of memories and peripherals (optional)
72 - Up to six regions for the Flash
73 - Up to two regions for the Data Flash
74 - Up to two regions for the SRAM
75 - Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel
76 - Secure Boot with SHA-based authentication (optional)
77 - Up to three debug access levels
78 - Up to three Chip Erase commands to erase part of or the entire embedded memories
79 - Unique 128-bit serial number
80 - SAM L11 Securely Key Provisioned (KPH) (optional)
81 - Key Provisioning using Root of Trust flow
82 - Security Software Framework using Kinibi-M™ Software Development Kit (SDK)
83
84#### 先进的模拟和触摸功能
85 - One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
86 - Two Analog Comparators (AC) with window compare function
87 - One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs
88 - Three Operational Amplifiers (OPAMP)
89 - One enhanced Peripheral Touch Controller (PTC):
90 - Up to 20 self-capacitance channels
91 - Up to 100 (10x10) mutual-capacitance channels
92 - Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
93 - Hardware noise filtering and noise signal desynchronization for high conducted immunity
94 - Driven Shield Plus for better noise immunity and moisture tolerance
95 - Parallel Acquisition through Polarity control
96 - Supports wake-up on touch from Standby Sleep mode
97
98#### 通信接口
99 - Up to three Serial Communication Interfaces (SERCOM) that can operate as:
100 - USART with full-duplex and single-wire half-duplex configuration
101 - I2C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the second instance
102 - Serial Peripheral Interface (SPI)
103 - ISO7816 on one instance (Available on 32-pin packages only)
104 - RS-485 on one instance (Available on 32-pin packages only)
105 - LIN Slave on one instance (Available on 32-pin packages only)
106 - Timers/Output Compare/Input Capture
107 - Three 16-bit Timers/Counters (TC), each configurable as:
108 - One 16-bit TC with two compare/capture channels
109 - One 8-bit TC with two compare/capture channels
110 - One 32-bit TC with two compare/capture channels, by using two TCs
111 - 32-bit Real-Time Counter (RTC) with clock/calendar functions
112 - Watchdog Timer (WDT) with Window mode
113 - Input/Output (I/O)
114 - Up to 25 programmable I/O lines
115 - Eight external interrupts (EIC)
116 - One non-maskable interrupt (NMI)
117 - One Configurable Custom Logic (CCL) that supports:
118 - Combinatorial logic functions, such as AND, NAND, OR, and NOR
119 - Sequential logic functions, such as Flip-Flop and Latches
120
121#### 汽车应用
122 - AEC - Q100 Grade 1 (-40°C to 125°C)
123 - Class-B safety library, IEC 60730 (future)
124
125#### 封装
126 - 24-pin VQFN(4*4mm/17 I/O pins)
127 - 32-pin VQFN(5*5mm/25 I/O pins)
128 - 32-pin TQFP(7*7mm/17 I/O pins)
129 - 32-pin WLCSP(2.79*2.79mm/25 I/O pins)
130
131#### 官方开发板信息
132- [SAM L10 XPLAINED PRO](https://ww1.microchip.com/downloads/en/Appnotes/Getting-Started-with-SAM%20L10L11-Xplained-Pro-DS00002722A.pdf)