1 /** 2 * \file 3 * 4 * \brief Component description for PM 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-31T14:29:25Z */ 31 #ifndef _SAML10_PM_COMPONENT_H_ 32 #define _SAML10_PM_COMPONENT_H_ 33 #define _SAML10_PM_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAML_SAML10 Power Manager 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR PM */ 40 /* ========================================================================== */ 41 42 #define PM_U2240 /**< (PM) Module ID */ 43 #define REV_PM 0x310 /**< (PM) Module revision */ 44 45 /* -------- PM_SLEEPCFG : (PM Offset: 0x01) (R/W 8) Sleep Configuration -------- */ 46 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 47 typedef union { 48 struct { 49 uint8_t SLEEPMODE:3; /**< bit: 0..2 Sleep Mode */ 50 uint8_t :5; /**< bit: 3..7 Reserved */ 51 } bit; /**< Structure used for bit access */ 52 uint8_t reg; /**< Type used for register access */ 53 } PM_SLEEPCFG_Type; 54 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define PM_SLEEPCFG_OFFSET (0x01) /**< (PM_SLEEPCFG) Sleep Configuration Offset */ 57 #define PM_SLEEPCFG_RESETVALUE _U_(0x02) /**< (PM_SLEEPCFG) Sleep Configuration Reset Value */ 58 59 #define PM_SLEEPCFG_SLEEPMODE_Pos 0 /**< (PM_SLEEPCFG) Sleep Mode Position */ 60 #define PM_SLEEPCFG_SLEEPMODE_Msk (_U_(0x7) << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) Sleep Mode Mask */ 61 #define PM_SLEEPCFG_SLEEPMODE(value) (PM_SLEEPCFG_SLEEPMODE_Msk & ((value) << PM_SLEEPCFG_SLEEPMODE_Pos)) 62 #define PM_SLEEPCFG_SLEEPMODE_IDLE_Val _U_(0x2) /**< (PM_SLEEPCFG) CPU, AHB, APB clocks are OFF */ 63 #define PM_SLEEPCFG_SLEEPMODE_STANDBY_Val _U_(0x4) /**< (PM_SLEEPCFG) All Clocks are OFF */ 64 #define PM_SLEEPCFG_SLEEPMODE_OFF_Val _U_(0x6) /**< (PM_SLEEPCFG) All power domains are powered OFF */ 65 #define PM_SLEEPCFG_SLEEPMODE_IDLE (PM_SLEEPCFG_SLEEPMODE_IDLE_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) CPU, AHB, APB clocks are OFF Position */ 66 #define PM_SLEEPCFG_SLEEPMODE_STANDBY (PM_SLEEPCFG_SLEEPMODE_STANDBY_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) All Clocks are OFF Position */ 67 #define PM_SLEEPCFG_SLEEPMODE_OFF (PM_SLEEPCFG_SLEEPMODE_OFF_Val << PM_SLEEPCFG_SLEEPMODE_Pos) /**< (PM_SLEEPCFG) All power domains are powered OFF Position */ 68 #define PM_SLEEPCFG_MASK _U_(0x07) /**< \deprecated (PM_SLEEPCFG) Register MASK (Use PM_SLEEPCFG_Msk instead) */ 69 #define PM_SLEEPCFG_Msk _U_(0x07) /**< (PM_SLEEPCFG) Register Mask */ 70 71 72 /* -------- PM_PLCFG : (PM Offset: 0x02) (R/W 8) Performance Level Configuration -------- */ 73 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 74 typedef union { 75 struct { 76 uint8_t PLSEL:2; /**< bit: 0..1 Performance Level Select */ 77 uint8_t :5; /**< bit: 2..6 Reserved */ 78 uint8_t PLDIS:1; /**< bit: 7 Performance Level Disable */ 79 } bit; /**< Structure used for bit access */ 80 uint8_t reg; /**< Type used for register access */ 81 } PM_PLCFG_Type; 82 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 83 84 #define PM_PLCFG_OFFSET (0x02) /**< (PM_PLCFG) Performance Level Configuration Offset */ 85 #define PM_PLCFG_RESETVALUE _U_(0x00) /**< (PM_PLCFG) Performance Level Configuration Reset Value */ 86 87 #define PM_PLCFG_PLSEL_Pos 0 /**< (PM_PLCFG) Performance Level Select Position */ 88 #define PM_PLCFG_PLSEL_Msk (_U_(0x3) << PM_PLCFG_PLSEL_Pos) /**< (PM_PLCFG) Performance Level Select Mask */ 89 #define PM_PLCFG_PLSEL(value) (PM_PLCFG_PLSEL_Msk & ((value) << PM_PLCFG_PLSEL_Pos)) 90 #define PM_PLCFG_PLSEL_PL0_Val _U_(0x0) /**< (PM_PLCFG) Performance Level 0 */ 91 #define PM_PLCFG_PLSEL_PL2_Val _U_(0x2) /**< (PM_PLCFG) Performance Level 2 */ 92 #define PM_PLCFG_PLSEL_PL0 (PM_PLCFG_PLSEL_PL0_Val << PM_PLCFG_PLSEL_Pos) /**< (PM_PLCFG) Performance Level 0 Position */ 93 #define PM_PLCFG_PLSEL_PL2 (PM_PLCFG_PLSEL_PL2_Val << PM_PLCFG_PLSEL_Pos) /**< (PM_PLCFG) Performance Level 2 Position */ 94 #define PM_PLCFG_PLDIS_Pos 7 /**< (PM_PLCFG) Performance Level Disable Position */ 95 #define PM_PLCFG_PLDIS_Msk (_U_(0x1) << PM_PLCFG_PLDIS_Pos) /**< (PM_PLCFG) Performance Level Disable Mask */ 96 #define PM_PLCFG_PLDIS PM_PLCFG_PLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_PLCFG_PLDIS_Msk instead */ 97 #define PM_PLCFG_MASK _U_(0x83) /**< \deprecated (PM_PLCFG) Register MASK (Use PM_PLCFG_Msk instead) */ 98 #define PM_PLCFG_Msk _U_(0x83) /**< (PM_PLCFG) Register Mask */ 99 100 101 /* -------- PM_PWCFG : (PM Offset: 0x03) (R/W 8) Power Configuration -------- */ 102 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 103 typedef union { 104 struct { 105 uint8_t RAMPSWC:2; /**< bit: 0..1 RAM Power Switch Configuration */ 106 uint8_t :6; /**< bit: 2..7 Reserved */ 107 } bit; /**< Structure used for bit access */ 108 uint8_t reg; /**< Type used for register access */ 109 } PM_PWCFG_Type; 110 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 #define PM_PWCFG_OFFSET (0x03) /**< (PM_PWCFG) Power Configuration Offset */ 113 #define PM_PWCFG_RESETVALUE _U_(0x00) /**< (PM_PWCFG) Power Configuration Reset Value */ 114 115 #define PM_PWCFG_RAMPSWC_Pos 0 /**< (PM_PWCFG) RAM Power Switch Configuration Position */ 116 #define PM_PWCFG_RAMPSWC_Msk (_U_(0x3) << PM_PWCFG_RAMPSWC_Pos) /**< (PM_PWCFG) RAM Power Switch Configuration Mask */ 117 #define PM_PWCFG_RAMPSWC(value) (PM_PWCFG_RAMPSWC_Msk & ((value) << PM_PWCFG_RAMPSWC_Pos)) 118 #define PM_PWCFG_RAMPSWC_16KB_Val _U_(0x0) /**< (PM_PWCFG) 16KB Available */ 119 #define PM_PWCFG_RAMPSWC_12KB_Val _U_(0x1) /**< (PM_PWCFG) 12KB Available */ 120 #define PM_PWCFG_RAMPSWC_8KB_Val _U_(0x2) /**< (PM_PWCFG) 8KB Available */ 121 #define PM_PWCFG_RAMPSWC_4KB_Val _U_(0x3) /**< (PM_PWCFG) 4KB Available */ 122 #define PM_PWCFG_RAMPSWC_16KB (PM_PWCFG_RAMPSWC_16KB_Val << PM_PWCFG_RAMPSWC_Pos) /**< (PM_PWCFG) 16KB Available Position */ 123 #define PM_PWCFG_RAMPSWC_12KB (PM_PWCFG_RAMPSWC_12KB_Val << PM_PWCFG_RAMPSWC_Pos) /**< (PM_PWCFG) 12KB Available Position */ 124 #define PM_PWCFG_RAMPSWC_8KB (PM_PWCFG_RAMPSWC_8KB_Val << PM_PWCFG_RAMPSWC_Pos) /**< (PM_PWCFG) 8KB Available Position */ 125 #define PM_PWCFG_RAMPSWC_4KB (PM_PWCFG_RAMPSWC_4KB_Val << PM_PWCFG_RAMPSWC_Pos) /**< (PM_PWCFG) 4KB Available Position */ 126 #define PM_PWCFG_MASK _U_(0x03) /**< \deprecated (PM_PWCFG) Register MASK (Use PM_PWCFG_Msk instead) */ 127 #define PM_PWCFG_Msk _U_(0x03) /**< (PM_PWCFG) Register Mask */ 128 129 130 /* -------- PM_INTENCLR : (PM Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 131 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 struct { 134 uint8_t PLRDY:1; /**< bit: 0 Performance Level Interrupt Enable */ 135 uint8_t :7; /**< bit: 1..7 Reserved */ 136 } bit; /**< Structure used for bit access */ 137 uint8_t reg; /**< Type used for register access */ 138 } PM_INTENCLR_Type; 139 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #define PM_INTENCLR_OFFSET (0x04) /**< (PM_INTENCLR) Interrupt Enable Clear Offset */ 142 #define PM_INTENCLR_RESETVALUE _U_(0x00) /**< (PM_INTENCLR) Interrupt Enable Clear Reset Value */ 143 144 #define PM_INTENCLR_PLRDY_Pos 0 /**< (PM_INTENCLR) Performance Level Interrupt Enable Position */ 145 #define PM_INTENCLR_PLRDY_Msk (_U_(0x1) << PM_INTENCLR_PLRDY_Pos) /**< (PM_INTENCLR) Performance Level Interrupt Enable Mask */ 146 #define PM_INTENCLR_PLRDY PM_INTENCLR_PLRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_INTENCLR_PLRDY_Msk instead */ 147 #define PM_INTENCLR_MASK _U_(0x01) /**< \deprecated (PM_INTENCLR) Register MASK (Use PM_INTENCLR_Msk instead) */ 148 #define PM_INTENCLR_Msk _U_(0x01) /**< (PM_INTENCLR) Register Mask */ 149 150 151 /* -------- PM_INTENSET : (PM Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 152 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 153 typedef union { 154 struct { 155 uint8_t PLRDY:1; /**< bit: 0 Performance Level Ready interrupt Enable */ 156 uint8_t :7; /**< bit: 1..7 Reserved */ 157 } bit; /**< Structure used for bit access */ 158 uint8_t reg; /**< Type used for register access */ 159 } PM_INTENSET_Type; 160 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 161 162 #define PM_INTENSET_OFFSET (0x05) /**< (PM_INTENSET) Interrupt Enable Set Offset */ 163 #define PM_INTENSET_RESETVALUE _U_(0x00) /**< (PM_INTENSET) Interrupt Enable Set Reset Value */ 164 165 #define PM_INTENSET_PLRDY_Pos 0 /**< (PM_INTENSET) Performance Level Ready interrupt Enable Position */ 166 #define PM_INTENSET_PLRDY_Msk (_U_(0x1) << PM_INTENSET_PLRDY_Pos) /**< (PM_INTENSET) Performance Level Ready interrupt Enable Mask */ 167 #define PM_INTENSET_PLRDY PM_INTENSET_PLRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_INTENSET_PLRDY_Msk instead */ 168 #define PM_INTENSET_MASK _U_(0x01) /**< \deprecated (PM_INTENSET) Register MASK (Use PM_INTENSET_Msk instead) */ 169 #define PM_INTENSET_Msk _U_(0x01) /**< (PM_INTENSET) Register Mask */ 170 171 172 /* -------- PM_INTFLAG : (PM Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 173 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 174 typedef union { // __I to avoid read-modify-write on write-to-clear register 175 struct { 176 __I uint8_t PLRDY:1; /**< bit: 0 Performance Level Ready */ 177 __I uint8_t :7; /**< bit: 1..7 Reserved */ 178 } bit; /**< Structure used for bit access */ 179 uint8_t reg; /**< Type used for register access */ 180 } PM_INTFLAG_Type; 181 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 182 183 #define PM_INTFLAG_OFFSET (0x06) /**< (PM_INTFLAG) Interrupt Flag Status and Clear Offset */ 184 #define PM_INTFLAG_RESETVALUE _U_(0x00) /**< (PM_INTFLAG) Interrupt Flag Status and Clear Reset Value */ 185 186 #define PM_INTFLAG_PLRDY_Pos 0 /**< (PM_INTFLAG) Performance Level Ready Position */ 187 #define PM_INTFLAG_PLRDY_Msk (_U_(0x1) << PM_INTFLAG_PLRDY_Pos) /**< (PM_INTFLAG) Performance Level Ready Mask */ 188 #define PM_INTFLAG_PLRDY PM_INTFLAG_PLRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_INTFLAG_PLRDY_Msk instead */ 189 #define PM_INTFLAG_MASK _U_(0x01) /**< \deprecated (PM_INTFLAG) Register MASK (Use PM_INTFLAG_Msk instead) */ 190 #define PM_INTFLAG_Msk _U_(0x01) /**< (PM_INTFLAG) Register Mask */ 191 192 193 /* -------- PM_STDBYCFG : (PM Offset: 0x08) (R/W 16) Standby Configuration -------- */ 194 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 195 typedef union { 196 struct { 197 uint16_t PDCFG:1; /**< bit: 0 Power Domain Configuration */ 198 uint16_t :3; /**< bit: 1..3 Reserved */ 199 uint16_t DPGPDSW:1; /**< bit: 4 Dynamic Power Gating for PDSW */ 200 uint16_t :1; /**< bit: 5 Reserved */ 201 uint16_t VREGSMOD:2; /**< bit: 6..7 Voltage Regulator Standby mode */ 202 uint16_t :2; /**< bit: 8..9 Reserved */ 203 uint16_t BBIASHS:1; /**< bit: 10 Back Bias for HSRAM */ 204 uint16_t :1; /**< bit: 11 Reserved */ 205 uint16_t BBIASTR:1; /**< bit: 12 Back Bias for Trust RAM */ 206 uint16_t :3; /**< bit: 13..15 Reserved */ 207 } bit; /**< Structure used for bit access */ 208 uint16_t reg; /**< Type used for register access */ 209 } PM_STDBYCFG_Type; 210 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 211 212 #define PM_STDBYCFG_OFFSET (0x08) /**< (PM_STDBYCFG) Standby Configuration Offset */ 213 #define PM_STDBYCFG_RESETVALUE _U_(0x00) /**< (PM_STDBYCFG) Standby Configuration Reset Value */ 214 215 #define PM_STDBYCFG_PDCFG_Pos 0 /**< (PM_STDBYCFG) Power Domain Configuration Position */ 216 #define PM_STDBYCFG_PDCFG_Msk (_U_(0x1) << PM_STDBYCFG_PDCFG_Pos) /**< (PM_STDBYCFG) Power Domain Configuration Mask */ 217 #define PM_STDBYCFG_PDCFG PM_STDBYCFG_PDCFG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_STDBYCFG_PDCFG_Msk instead */ 218 #define PM_STDBYCFG_PDCFG_DEFAULT_Val _U_(0x0) /**< (PM_STDBYCFG) PDSW power domain switching is handled by hardware. */ 219 #define PM_STDBYCFG_PDCFG_PDSW_Val _U_(0x1) /**< (PM_STDBYCFG) PDSW is forced ACTIVE. */ 220 #define PM_STDBYCFG_PDCFG_DEFAULT (PM_STDBYCFG_PDCFG_DEFAULT_Val << PM_STDBYCFG_PDCFG_Pos) /**< (PM_STDBYCFG) PDSW power domain switching is handled by hardware. Position */ 221 #define PM_STDBYCFG_PDCFG_PDSW (PM_STDBYCFG_PDCFG_PDSW_Val << PM_STDBYCFG_PDCFG_Pos) /**< (PM_STDBYCFG) PDSW is forced ACTIVE. Position */ 222 #define PM_STDBYCFG_DPGPDSW_Pos 4 /**< (PM_STDBYCFG) Dynamic Power Gating for PDSW Position */ 223 #define PM_STDBYCFG_DPGPDSW_Msk (_U_(0x1) << PM_STDBYCFG_DPGPDSW_Pos) /**< (PM_STDBYCFG) Dynamic Power Gating for PDSW Mask */ 224 #define PM_STDBYCFG_DPGPDSW PM_STDBYCFG_DPGPDSW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_STDBYCFG_DPGPDSW_Msk instead */ 225 #define PM_STDBYCFG_DPGPDSW_0_Val _U_(0x0) /**< (PM_STDBYCFG) Dynamic Power Gating disabled */ 226 #define PM_STDBYCFG_DPGPDSW_1_Val _U_(0x1) /**< (PM_STDBYCFG) Dynamic Power Gating enabled */ 227 #define PM_STDBYCFG_DPGPDSW_0 (PM_STDBYCFG_DPGPDSW_0_Val << PM_STDBYCFG_DPGPDSW_Pos) /**< (PM_STDBYCFG) Dynamic Power Gating disabled Position */ 228 #define PM_STDBYCFG_DPGPDSW_1 (PM_STDBYCFG_DPGPDSW_1_Val << PM_STDBYCFG_DPGPDSW_Pos) /**< (PM_STDBYCFG) Dynamic Power Gating enabled Position */ 229 #define PM_STDBYCFG_VREGSMOD_Pos 6 /**< (PM_STDBYCFG) Voltage Regulator Standby mode Position */ 230 #define PM_STDBYCFG_VREGSMOD_Msk (_U_(0x3) << PM_STDBYCFG_VREGSMOD_Pos) /**< (PM_STDBYCFG) Voltage Regulator Standby mode Mask */ 231 #define PM_STDBYCFG_VREGSMOD(value) (PM_STDBYCFG_VREGSMOD_Msk & ((value) << PM_STDBYCFG_VREGSMOD_Pos)) 232 #define PM_STDBYCFG_VREGSMOD_AUTO_Val _U_(0x0) /**< (PM_STDBYCFG) Automatic mode */ 233 #define PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val _U_(0x1) /**< (PM_STDBYCFG) Performance oriented */ 234 #define PM_STDBYCFG_VREGSMOD_LP_Val _U_(0x2) /**< (PM_STDBYCFG) Low Power oriented */ 235 #define PM_STDBYCFG_VREGSMOD_AUTO (PM_STDBYCFG_VREGSMOD_AUTO_Val << PM_STDBYCFG_VREGSMOD_Pos) /**< (PM_STDBYCFG) Automatic mode Position */ 236 #define PM_STDBYCFG_VREGSMOD_PERFORMANCE (PM_STDBYCFG_VREGSMOD_PERFORMANCE_Val << PM_STDBYCFG_VREGSMOD_Pos) /**< (PM_STDBYCFG) Performance oriented Position */ 237 #define PM_STDBYCFG_VREGSMOD_LP (PM_STDBYCFG_VREGSMOD_LP_Val << PM_STDBYCFG_VREGSMOD_Pos) /**< (PM_STDBYCFG) Low Power oriented Position */ 238 #define PM_STDBYCFG_BBIASHS_Pos 10 /**< (PM_STDBYCFG) Back Bias for HSRAM Position */ 239 #define PM_STDBYCFG_BBIASHS_Msk (_U_(0x1) << PM_STDBYCFG_BBIASHS_Pos) /**< (PM_STDBYCFG) Back Bias for HSRAM Mask */ 240 #define PM_STDBYCFG_BBIASHS PM_STDBYCFG_BBIASHS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_STDBYCFG_BBIASHS_Msk instead */ 241 #define PM_STDBYCFG_BBIASTR_Pos 12 /**< (PM_STDBYCFG) Back Bias for Trust RAM Position */ 242 #define PM_STDBYCFG_BBIASTR_Msk (_U_(0x1) << PM_STDBYCFG_BBIASTR_Pos) /**< (PM_STDBYCFG) Back Bias for Trust RAM Mask */ 243 #define PM_STDBYCFG_BBIASTR PM_STDBYCFG_BBIASTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use PM_STDBYCFG_BBIASTR_Msk instead */ 244 #define PM_STDBYCFG_MASK _U_(0x14D1) /**< \deprecated (PM_STDBYCFG) Register MASK (Use PM_STDBYCFG_Msk instead) */ 245 #define PM_STDBYCFG_Msk _U_(0x14D1) /**< (PM_STDBYCFG) Register Mask */ 246 247 248 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 249 /** \brief PM hardware registers */ 250 typedef struct { /* Power Manager */ 251 __I uint8_t Reserved1[1]; 252 __IO PM_SLEEPCFG_Type SLEEPCFG; /**< Offset: 0x01 (R/W 8) Sleep Configuration */ 253 __IO PM_PLCFG_Type PLCFG; /**< Offset: 0x02 (R/W 8) Performance Level Configuration */ 254 __IO PM_PWCFG_Type PWCFG; /**< Offset: 0x03 (R/W 8) Power Configuration */ 255 __IO PM_INTENCLR_Type INTENCLR; /**< Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 256 __IO PM_INTENSET_Type INTENSET; /**< Offset: 0x05 (R/W 8) Interrupt Enable Set */ 257 __IO PM_INTFLAG_Type INTFLAG; /**< Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 258 __I uint8_t Reserved2[1]; 259 __IO PM_STDBYCFG_Type STDBYCFG; /**< Offset: 0x08 (R/W 16) Standby Configuration */ 260 } Pm; 261 262 263 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 264 /** @} end of Power Manager */ 265 266 #endif /* _SAML10_PM_COMPONENT_H_ */ 267