1 /** 2 * \file 3 * 4 * \brief Instance description for GCLK 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-31T14:29:25Z */ 31 #ifndef _SAML10_GCLK_INSTANCE_H_ 32 #define _SAML10_GCLK_INSTANCE_H_ 33 34 /* ========== Register definition for GCLK peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_GCLK_CTRLA (0x40001C00) /**< (GCLK) Control */ 38 #define REG_GCLK_SYNCBUSY (0x40001C04) /**< (GCLK) Synchronization Busy */ 39 #define REG_GCLK_GENCTRL (0x40001C20) /**< (GCLK) Generic Clock Generator Control */ 40 #define REG_GCLK_GENCTRL0 (0x40001C20) /**< (GCLK) Generic Clock Generator Control 0 */ 41 #define REG_GCLK_GENCTRL1 (0x40001C24) /**< (GCLK) Generic Clock Generator Control 1 */ 42 #define REG_GCLK_GENCTRL2 (0x40001C28) /**< (GCLK) Generic Clock Generator Control 2 */ 43 #define REG_GCLK_GENCTRL3 (0x40001C2C) /**< (GCLK) Generic Clock Generator Control 3 */ 44 #define REG_GCLK_GENCTRL4 (0x40001C30) /**< (GCLK) Generic Clock Generator Control 4 */ 45 #define REG_GCLK_PCHCTRL (0x40001C80) /**< (GCLK) Peripheral Clock Control */ 46 #define REG_GCLK_PCHCTRL0 (0x40001C80) /**< (GCLK) Peripheral Clock Control 0 */ 47 #define REG_GCLK_PCHCTRL1 (0x40001C84) /**< (GCLK) Peripheral Clock Control 1 */ 48 #define REG_GCLK_PCHCTRL2 (0x40001C88) /**< (GCLK) Peripheral Clock Control 2 */ 49 #define REG_GCLK_PCHCTRL3 (0x40001C8C) /**< (GCLK) Peripheral Clock Control 3 */ 50 #define REG_GCLK_PCHCTRL4 (0x40001C90) /**< (GCLK) Peripheral Clock Control 4 */ 51 #define REG_GCLK_PCHCTRL5 (0x40001C94) /**< (GCLK) Peripheral Clock Control 5 */ 52 #define REG_GCLK_PCHCTRL6 (0x40001C98) /**< (GCLK) Peripheral Clock Control 6 */ 53 #define REG_GCLK_PCHCTRL7 (0x40001C9C) /**< (GCLK) Peripheral Clock Control 7 */ 54 #define REG_GCLK_PCHCTRL8 (0x40001CA0) /**< (GCLK) Peripheral Clock Control 8 */ 55 #define REG_GCLK_PCHCTRL9 (0x40001CA4) /**< (GCLK) Peripheral Clock Control 9 */ 56 #define REG_GCLK_PCHCTRL10 (0x40001CA8) /**< (GCLK) Peripheral Clock Control 10 */ 57 #define REG_GCLK_PCHCTRL11 (0x40001CAC) /**< (GCLK) Peripheral Clock Control 11 */ 58 #define REG_GCLK_PCHCTRL12 (0x40001CB0) /**< (GCLK) Peripheral Clock Control 12 */ 59 #define REG_GCLK_PCHCTRL13 (0x40001CB4) /**< (GCLK) Peripheral Clock Control 13 */ 60 #define REG_GCLK_PCHCTRL14 (0x40001CB8) /**< (GCLK) Peripheral Clock Control 14 */ 61 #define REG_GCLK_PCHCTRL15 (0x40001CBC) /**< (GCLK) Peripheral Clock Control 15 */ 62 #define REG_GCLK_PCHCTRL16 (0x40001CC0) /**< (GCLK) Peripheral Clock Control 16 */ 63 #define REG_GCLK_PCHCTRL17 (0x40001CC4) /**< (GCLK) Peripheral Clock Control 17 */ 64 #define REG_GCLK_PCHCTRL18 (0x40001CC8) /**< (GCLK) Peripheral Clock Control 18 */ 65 #define REG_GCLK_PCHCTRL19 (0x40001CCC) /**< (GCLK) Peripheral Clock Control 19 */ 66 #define REG_GCLK_PCHCTRL20 (0x40001CD0) /**< (GCLK) Peripheral Clock Control 20 */ 67 68 #else 69 70 #define REG_GCLK_CTRLA (*(__IO uint8_t*)0x40001C00U) /**< (GCLK) Control */ 71 #define REG_GCLK_SYNCBUSY (*(__I uint32_t*)0x40001C04U) /**< (GCLK) Synchronization Busy */ 72 #define REG_GCLK_GENCTRL (*(__IO uint32_t*)0x40001C20U) /**< (GCLK) Generic Clock Generator Control */ 73 #define REG_GCLK_GENCTRL0 (*(__IO uint32_t*)0x40001C20U) /**< (GCLK) Generic Clock Generator Control 0 */ 74 #define REG_GCLK_GENCTRL1 (*(__IO uint32_t*)0x40001C24U) /**< (GCLK) Generic Clock Generator Control 1 */ 75 #define REG_GCLK_GENCTRL2 (*(__IO uint32_t*)0x40001C28U) /**< (GCLK) Generic Clock Generator Control 2 */ 76 #define REG_GCLK_GENCTRL3 (*(__IO uint32_t*)0x40001C2CU) /**< (GCLK) Generic Clock Generator Control 3 */ 77 #define REG_GCLK_GENCTRL4 (*(__IO uint32_t*)0x40001C30U) /**< (GCLK) Generic Clock Generator Control 4 */ 78 #define REG_GCLK_PCHCTRL (*(__IO uint32_t*)0x40001C80U) /**< (GCLK) Peripheral Clock Control */ 79 #define REG_GCLK_PCHCTRL0 (*(__IO uint32_t*)0x40001C80U) /**< (GCLK) Peripheral Clock Control 0 */ 80 #define REG_GCLK_PCHCTRL1 (*(__IO uint32_t*)0x40001C84U) /**< (GCLK) Peripheral Clock Control 1 */ 81 #define REG_GCLK_PCHCTRL2 (*(__IO uint32_t*)0x40001C88U) /**< (GCLK) Peripheral Clock Control 2 */ 82 #define REG_GCLK_PCHCTRL3 (*(__IO uint32_t*)0x40001C8CU) /**< (GCLK) Peripheral Clock Control 3 */ 83 #define REG_GCLK_PCHCTRL4 (*(__IO uint32_t*)0x40001C90U) /**< (GCLK) Peripheral Clock Control 4 */ 84 #define REG_GCLK_PCHCTRL5 (*(__IO uint32_t*)0x40001C94U) /**< (GCLK) Peripheral Clock Control 5 */ 85 #define REG_GCLK_PCHCTRL6 (*(__IO uint32_t*)0x40001C98U) /**< (GCLK) Peripheral Clock Control 6 */ 86 #define REG_GCLK_PCHCTRL7 (*(__IO uint32_t*)0x40001C9CU) /**< (GCLK) Peripheral Clock Control 7 */ 87 #define REG_GCLK_PCHCTRL8 (*(__IO uint32_t*)0x40001CA0U) /**< (GCLK) Peripheral Clock Control 8 */ 88 #define REG_GCLK_PCHCTRL9 (*(__IO uint32_t*)0x40001CA4U) /**< (GCLK) Peripheral Clock Control 9 */ 89 #define REG_GCLK_PCHCTRL10 (*(__IO uint32_t*)0x40001CA8U) /**< (GCLK) Peripheral Clock Control 10 */ 90 #define REG_GCLK_PCHCTRL11 (*(__IO uint32_t*)0x40001CACU) /**< (GCLK) Peripheral Clock Control 11 */ 91 #define REG_GCLK_PCHCTRL12 (*(__IO uint32_t*)0x40001CB0U) /**< (GCLK) Peripheral Clock Control 12 */ 92 #define REG_GCLK_PCHCTRL13 (*(__IO uint32_t*)0x40001CB4U) /**< (GCLK) Peripheral Clock Control 13 */ 93 #define REG_GCLK_PCHCTRL14 (*(__IO uint32_t*)0x40001CB8U) /**< (GCLK) Peripheral Clock Control 14 */ 94 #define REG_GCLK_PCHCTRL15 (*(__IO uint32_t*)0x40001CBCU) /**< (GCLK) Peripheral Clock Control 15 */ 95 #define REG_GCLK_PCHCTRL16 (*(__IO uint32_t*)0x40001CC0U) /**< (GCLK) Peripheral Clock Control 16 */ 96 #define REG_GCLK_PCHCTRL17 (*(__IO uint32_t*)0x40001CC4U) /**< (GCLK) Peripheral Clock Control 17 */ 97 #define REG_GCLK_PCHCTRL18 (*(__IO uint32_t*)0x40001CC8U) /**< (GCLK) Peripheral Clock Control 18 */ 98 #define REG_GCLK_PCHCTRL19 (*(__IO uint32_t*)0x40001CCCU) /**< (GCLK) Peripheral Clock Control 19 */ 99 #define REG_GCLK_PCHCTRL20 (*(__IO uint32_t*)0x40001CD0U) /**< (GCLK) Peripheral Clock Control 20 */ 100 101 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 /* ========== Instance Parameter definitions for GCLK peripheral ========== */ 104 #define GCLK_GENDIV_BITS 16 105 #define GCLK_GEN_BITS 3 106 #define GCLK_GEN_NUM 5 /* Number of Generic Clock Generators */ 107 #define GCLK_GEN_NUM_MSB 4 /* Number of Generic Clock Generators - 1 */ 108 #define GCLK_GEN_SOURCE_NUM_MSB 7 /* Number of Generic Clock Sources - 1 */ 109 #define GCLK_NUM 21 /* Number of Generic Clock Users */ 110 #define GCLK_SOURCE_BITS 3 111 #define GCLK_SOURCE_NUM 8 /* Number of Generic Clock Sources */ 112 #define GCLK_INSTANCE_ID 7 113 114 #endif /* _SAML10_GCLK_INSTANCE_ */ 115