1 /** 2 * \file 3 * 4 * \brief Instance description for RTC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-31T14:29:25Z */ 31 #ifndef _SAML10_RTC_INSTANCE_H_ 32 #define _SAML10_RTC_INSTANCE_H_ 33 34 /* ========== Register definition for RTC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_RTC_DBGCTRL (0x4000240E) /**< (RTC) Debug Control */ 38 #define REG_RTC_FREQCORR (0x40002414) /**< (RTC) Frequency Correction */ 39 #define REG_RTC_GP (0x40002440) /**< (RTC) General Purpose */ 40 #define REG_RTC_GP0 (0x40002440) /**< (RTC) General Purpose 0 */ 41 #define REG_RTC_GP1 (0x40002444) /**< (RTC) General Purpose 1 */ 42 #define REG_RTC_TAMPCTRL (0x40002460) /**< (RTC) Tamper Control */ 43 #define REG_RTC_TAMPID (0x40002468) /**< (RTC) Tamper ID */ 44 #define REG_RTC_TAMPCTRLB (0x4000246C) /**< (RTC) Tamper Control B */ 45 #define REG_RTC_MODE0_CTRLA (0x40002400) /**< (RTC) MODE0 Control A */ 46 #define REG_RTC_MODE0_CTRLB (0x40002402) /**< (RTC) MODE0 Control B */ 47 #define REG_RTC_MODE0_EVCTRL (0x40002404) /**< (RTC) MODE0 Event Control */ 48 #define REG_RTC_MODE0_INTENCLR (0x40002408) /**< (RTC) MODE0 Interrupt Enable Clear */ 49 #define REG_RTC_MODE0_INTENSET (0x4000240A) /**< (RTC) MODE0 Interrupt Enable Set */ 50 #define REG_RTC_MODE0_INTFLAG (0x4000240C) /**< (RTC) MODE0 Interrupt Flag Status and Clear */ 51 #define REG_RTC_MODE0_SYNCBUSY (0x40002410) /**< (RTC) MODE0 Synchronization Busy Status */ 52 #define REG_RTC_MODE0_COUNT (0x40002418) /**< (RTC) MODE0 Counter Value */ 53 #define REG_RTC_MODE0_COMP (0x40002420) /**< (RTC) MODE0 Compare n Value */ 54 #define REG_RTC_MODE0_COMP0 (0x40002420) /**< (RTC) MODE0 Compare 0 Value */ 55 #define REG_RTC_MODE0_TIMESTAMP (0x40002464) /**< (RTC) MODE0 Timestamp */ 56 #define REG_RTC_MODE1_CTRLA (0x40002400) /**< (RTC) MODE1 Control A */ 57 #define REG_RTC_MODE1_CTRLB (0x40002402) /**< (RTC) MODE1 Control B */ 58 #define REG_RTC_MODE1_EVCTRL (0x40002404) /**< (RTC) MODE1 Event Control */ 59 #define REG_RTC_MODE1_INTENCLR (0x40002408) /**< (RTC) MODE1 Interrupt Enable Clear */ 60 #define REG_RTC_MODE1_INTENSET (0x4000240A) /**< (RTC) MODE1 Interrupt Enable Set */ 61 #define REG_RTC_MODE1_INTFLAG (0x4000240C) /**< (RTC) MODE1 Interrupt Flag Status and Clear */ 62 #define REG_RTC_MODE1_SYNCBUSY (0x40002410) /**< (RTC) MODE1 Synchronization Busy Status */ 63 #define REG_RTC_MODE1_COUNT (0x40002418) /**< (RTC) MODE1 Counter Value */ 64 #define REG_RTC_MODE1_PER (0x4000241C) /**< (RTC) MODE1 Counter Period */ 65 #define REG_RTC_MODE1_COMP (0x40002420) /**< (RTC) MODE1 Compare n Value */ 66 #define REG_RTC_MODE1_COMP0 (0x40002420) /**< (RTC) MODE1 Compare 0 Value */ 67 #define REG_RTC_MODE1_COMP1 (0x40002422) /**< (RTC) MODE1 Compare 1 Value */ 68 #define REG_RTC_MODE1_TIMESTAMP (0x40002464) /**< (RTC) MODE1 Timestamp */ 69 #define REG_RTC_MODE2_ALARM0 (0x40002420) /**< (RTC) MODE2_ALARM Alarm 0 Value */ 70 #define REG_RTC_MODE2_MASK0 (0x40002424) /**< (RTC) MODE2_ALARM Alarm 0 Mask */ 71 #define REG_RTC_MODE2_CTRLA (0x40002400) /**< (RTC) MODE2 Control A */ 72 #define REG_RTC_MODE2_CTRLB (0x40002402) /**< (RTC) MODE2 Control B */ 73 #define REG_RTC_MODE2_EVCTRL (0x40002404) /**< (RTC) MODE2 Event Control */ 74 #define REG_RTC_MODE2_INTENCLR (0x40002408) /**< (RTC) MODE2 Interrupt Enable Clear */ 75 #define REG_RTC_MODE2_INTENSET (0x4000240A) /**< (RTC) MODE2 Interrupt Enable Set */ 76 #define REG_RTC_MODE2_INTFLAG (0x4000240C) /**< (RTC) MODE2 Interrupt Flag Status and Clear */ 77 #define REG_RTC_MODE2_SYNCBUSY (0x40002410) /**< (RTC) MODE2 Synchronization Busy Status */ 78 #define REG_RTC_MODE2_CLOCK (0x40002418) /**< (RTC) MODE2 Clock Value */ 79 #define REG_RTC_MODE2_TIMESTAMP (0x40002464) /**< (RTC) MODE2 Timestamp */ 80 81 #else 82 83 #define REG_RTC_DBGCTRL (*(__IO uint8_t*)0x4000240EU) /**< (RTC) Debug Control */ 84 #define REG_RTC_FREQCORR (*(__IO uint8_t*)0x40002414U) /**< (RTC) Frequency Correction */ 85 #define REG_RTC_GP (*(__IO uint32_t*)0x40002440U) /**< (RTC) General Purpose */ 86 #define REG_RTC_GP0 (*(__IO uint32_t*)0x40002440U) /**< (RTC) General Purpose 0 */ 87 #define REG_RTC_GP1 (*(__IO uint32_t*)0x40002444U) /**< (RTC) General Purpose 1 */ 88 #define REG_RTC_TAMPCTRL (*(__IO uint32_t*)0x40002460U) /**< (RTC) Tamper Control */ 89 #define REG_RTC_TAMPID (*(__IO uint32_t*)0x40002468U) /**< (RTC) Tamper ID */ 90 #define REG_RTC_TAMPCTRLB (*(__IO uint32_t*)0x4000246CU) /**< (RTC) Tamper Control B */ 91 #define REG_RTC_MODE0_CTRLA (*(__IO uint16_t*)0x40002400U) /**< (RTC) MODE0 Control A */ 92 #define REG_RTC_MODE0_CTRLB (*(__IO uint16_t*)0x40002402U) /**< (RTC) MODE0 Control B */ 93 #define REG_RTC_MODE0_EVCTRL (*(__IO uint32_t*)0x40002404U) /**< (RTC) MODE0 Event Control */ 94 #define REG_RTC_MODE0_INTENCLR (*(__IO uint16_t*)0x40002408U) /**< (RTC) MODE0 Interrupt Enable Clear */ 95 #define REG_RTC_MODE0_INTENSET (*(__IO uint16_t*)0x4000240AU) /**< (RTC) MODE0 Interrupt Enable Set */ 96 #define REG_RTC_MODE0_INTFLAG (*(__IO uint16_t*)0x4000240CU) /**< (RTC) MODE0 Interrupt Flag Status and Clear */ 97 #define REG_RTC_MODE0_SYNCBUSY (*(__I uint32_t*)0x40002410U) /**< (RTC) MODE0 Synchronization Busy Status */ 98 #define REG_RTC_MODE0_COUNT (*(__IO uint32_t*)0x40002418U) /**< (RTC) MODE0 Counter Value */ 99 #define REG_RTC_MODE0_COMP (*(__IO uint32_t*)0x40002420U) /**< (RTC) MODE0 Compare n Value */ 100 #define REG_RTC_MODE0_COMP0 (*(__IO uint32_t*)0x40002420U) /**< (RTC) MODE0 Compare 0 Value */ 101 #define REG_RTC_MODE0_TIMESTAMP (*(__I uint32_t*)0x40002464U) /**< (RTC) MODE0 Timestamp */ 102 #define REG_RTC_MODE1_CTRLA (*(__IO uint16_t*)0x40002400U) /**< (RTC) MODE1 Control A */ 103 #define REG_RTC_MODE1_CTRLB (*(__IO uint16_t*)0x40002402U) /**< (RTC) MODE1 Control B */ 104 #define REG_RTC_MODE1_EVCTRL (*(__IO uint32_t*)0x40002404U) /**< (RTC) MODE1 Event Control */ 105 #define REG_RTC_MODE1_INTENCLR (*(__IO uint16_t*)0x40002408U) /**< (RTC) MODE1 Interrupt Enable Clear */ 106 #define REG_RTC_MODE1_INTENSET (*(__IO uint16_t*)0x4000240AU) /**< (RTC) MODE1 Interrupt Enable Set */ 107 #define REG_RTC_MODE1_INTFLAG (*(__IO uint16_t*)0x4000240CU) /**< (RTC) MODE1 Interrupt Flag Status and Clear */ 108 #define REG_RTC_MODE1_SYNCBUSY (*(__I uint32_t*)0x40002410U) /**< (RTC) MODE1 Synchronization Busy Status */ 109 #define REG_RTC_MODE1_COUNT (*(__IO uint16_t*)0x40002418U) /**< (RTC) MODE1 Counter Value */ 110 #define REG_RTC_MODE1_PER (*(__IO uint16_t*)0x4000241CU) /**< (RTC) MODE1 Counter Period */ 111 #define REG_RTC_MODE1_COMP (*(__IO uint16_t*)0x40002420U) /**< (RTC) MODE1 Compare n Value */ 112 #define REG_RTC_MODE1_COMP0 (*(__IO uint16_t*)0x40002420U) /**< (RTC) MODE1 Compare 0 Value */ 113 #define REG_RTC_MODE1_COMP1 (*(__IO uint16_t*)0x40002422U) /**< (RTC) MODE1 Compare 1 Value */ 114 #define REG_RTC_MODE1_TIMESTAMP (*(__I uint32_t*)0x40002464U) /**< (RTC) MODE1 Timestamp */ 115 #define REG_RTC_MODE2_ALARM0 (*(__IO uint32_t*)0x40002420U) /**< (RTC) MODE2_ALARM Alarm 0 Value */ 116 #define REG_RTC_MODE2_MASK0 (*(__IO uint8_t*)0x40002424U) /**< (RTC) MODE2_ALARM Alarm 0 Mask */ 117 #define REG_RTC_MODE2_CTRLA (*(__IO uint16_t*)0x40002400U) /**< (RTC) MODE2 Control A */ 118 #define REG_RTC_MODE2_CTRLB (*(__IO uint16_t*)0x40002402U) /**< (RTC) MODE2 Control B */ 119 #define REG_RTC_MODE2_EVCTRL (*(__IO uint32_t*)0x40002404U) /**< (RTC) MODE2 Event Control */ 120 #define REG_RTC_MODE2_INTENCLR (*(__IO uint16_t*)0x40002408U) /**< (RTC) MODE2 Interrupt Enable Clear */ 121 #define REG_RTC_MODE2_INTENSET (*(__IO uint16_t*)0x4000240AU) /**< (RTC) MODE2 Interrupt Enable Set */ 122 #define REG_RTC_MODE2_INTFLAG (*(__IO uint16_t*)0x4000240CU) /**< (RTC) MODE2 Interrupt Flag Status and Clear */ 123 #define REG_RTC_MODE2_SYNCBUSY (*(__I uint32_t*)0x40002410U) /**< (RTC) MODE2 Synchronization Busy Status */ 124 #define REG_RTC_MODE2_CLOCK (*(__IO uint32_t*)0x40002418U) /**< (RTC) MODE2 Clock Value */ 125 #define REG_RTC_MODE2_TIMESTAMP (*(__I uint32_t*)0x40002464U) /**< (RTC) MODE2 Timestamp */ 126 127 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 128 129 /* ========== Instance Parameter definitions for RTC peripheral ========== */ 130 #define RTC_DMAC_ID_TIMESTAMP 1 /* DMA RTC timestamp trigger */ 131 #define RTC_GPR_NUM 2 /* Number of General-Purpose Registers */ 132 #define RTC_NUM_OF_ALARMS 1 /* Number of Alarms */ 133 #define RTC_NUM_OF_BKREGS 0 /* Number of Backup Registers */ 134 #define RTC_NUM_OF_COMP16 2 /* Number of 16-bit Comparators */ 135 #define RTC_NUM_OF_COMP32 1 /* Number of 32-bit Comparators */ 136 #define RTC_NUM_OF_TAMPERS 4 /* Number of Tamper Inputs */ 137 #define RTC_PER_NUM 8 /* Number of Periodic Intervals */ 138 #define RTC_INSTANCE_ID 9 139 140 #endif /* _SAML10_RTC_INSTANCE_ */ 141