1 /** 2 * \file 3 * 4 * \brief Instance description for SERCOM2 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-31T14:29:25Z */ 31 #ifndef _SAML10_SERCOM2_INSTANCE_H_ 32 #define _SAML10_SERCOM2_INSTANCE_H_ 33 34 /* ========== Register definition for SERCOM2 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_SERCOM2_I2CM_CTRLA (0x42000C00) /**< (SERCOM2) I2CM Control A */ 38 #define REG_SERCOM2_I2CM_CTRLB (0x42000C04) /**< (SERCOM2) I2CM Control B */ 39 #define REG_SERCOM2_I2CM_BAUD (0x42000C0C) /**< (SERCOM2) I2CM Baud Rate */ 40 #define REG_SERCOM2_I2CM_INTENCLR (0x42000C14) /**< (SERCOM2) I2CM Interrupt Enable Clear */ 41 #define REG_SERCOM2_I2CM_INTENSET (0x42000C16) /**< (SERCOM2) I2CM Interrupt Enable Set */ 42 #define REG_SERCOM2_I2CM_INTFLAG (0x42000C18) /**< (SERCOM2) I2CM Interrupt Flag Status and Clear */ 43 #define REG_SERCOM2_I2CM_STATUS (0x42000C1A) /**< (SERCOM2) I2CM Status */ 44 #define REG_SERCOM2_I2CM_SYNCBUSY (0x42000C1C) /**< (SERCOM2) I2CM Synchronization Busy */ 45 #define REG_SERCOM2_I2CM_ADDR (0x42000C24) /**< (SERCOM2) I2CM Address */ 46 #define REG_SERCOM2_I2CM_DATA (0x42000C28) /**< (SERCOM2) I2CM Data */ 47 #define REG_SERCOM2_I2CM_DBGCTRL (0x42000C30) /**< (SERCOM2) I2CM Debug Control */ 48 #define REG_SERCOM2_I2CS_CTRLA (0x42000C00) /**< (SERCOM2) I2CS Control A */ 49 #define REG_SERCOM2_I2CS_CTRLB (0x42000C04) /**< (SERCOM2) I2CS Control B */ 50 #define REG_SERCOM2_I2CS_INTENCLR (0x42000C14) /**< (SERCOM2) I2CS Interrupt Enable Clear */ 51 #define REG_SERCOM2_I2CS_INTENSET (0x42000C16) /**< (SERCOM2) I2CS Interrupt Enable Set */ 52 #define REG_SERCOM2_I2CS_INTFLAG (0x42000C18) /**< (SERCOM2) I2CS Interrupt Flag Status and Clear */ 53 #define REG_SERCOM2_I2CS_STATUS (0x42000C1A) /**< (SERCOM2) I2CS Status */ 54 #define REG_SERCOM2_I2CS_SYNCBUSY (0x42000C1C) /**< (SERCOM2) I2CS Synchronization Busy */ 55 #define REG_SERCOM2_I2CS_ADDR (0x42000C24) /**< (SERCOM2) I2CS Address */ 56 #define REG_SERCOM2_I2CS_DATA (0x42000C28) /**< (SERCOM2) I2CS Data */ 57 #define REG_SERCOM2_SPI_CTRLA (0x42000C00) /**< (SERCOM2) SPI Control A */ 58 #define REG_SERCOM2_SPI_CTRLB (0x42000C04) /**< (SERCOM2) SPI Control B */ 59 #define REG_SERCOM2_SPI_BAUD (0x42000C0C) /**< (SERCOM2) SPI Baud Rate */ 60 #define REG_SERCOM2_SPI_INTENCLR (0x42000C14) /**< (SERCOM2) SPI Interrupt Enable Clear */ 61 #define REG_SERCOM2_SPI_INTENSET (0x42000C16) /**< (SERCOM2) SPI Interrupt Enable Set */ 62 #define REG_SERCOM2_SPI_INTFLAG (0x42000C18) /**< (SERCOM2) SPI Interrupt Flag Status and Clear */ 63 #define REG_SERCOM2_SPI_STATUS (0x42000C1A) /**< (SERCOM2) SPI Status */ 64 #define REG_SERCOM2_SPI_SYNCBUSY (0x42000C1C) /**< (SERCOM2) SPI Synchronization Busy */ 65 #define REG_SERCOM2_SPI_ADDR (0x42000C24) /**< (SERCOM2) SPI Address */ 66 #define REG_SERCOM2_SPI_DATA (0x42000C28) /**< (SERCOM2) SPI Data */ 67 #define REG_SERCOM2_SPI_DBGCTRL (0x42000C30) /**< (SERCOM2) SPI Debug Control */ 68 #define REG_SERCOM2_USART_CTRLA (0x42000C00) /**< (SERCOM2) USART Control A */ 69 #define REG_SERCOM2_USART_CTRLB (0x42000C04) /**< (SERCOM2) USART Control B */ 70 #define REG_SERCOM2_USART_CTRLC (0x42000C08) /**< (SERCOM2) USART Control C */ 71 #define REG_SERCOM2_USART_BAUD (0x42000C0C) /**< (SERCOM2) USART Baud Rate */ 72 #define REG_SERCOM2_USART_RXPL (0x42000C0E) /**< (SERCOM2) USART Receive Pulse Length */ 73 #define REG_SERCOM2_USART_INTENCLR (0x42000C14) /**< (SERCOM2) USART Interrupt Enable Clear */ 74 #define REG_SERCOM2_USART_INTENSET (0x42000C16) /**< (SERCOM2) USART Interrupt Enable Set */ 75 #define REG_SERCOM2_USART_INTFLAG (0x42000C18) /**< (SERCOM2) USART Interrupt Flag Status and Clear */ 76 #define REG_SERCOM2_USART_STATUS (0x42000C1A) /**< (SERCOM2) USART Status */ 77 #define REG_SERCOM2_USART_SYNCBUSY (0x42000C1C) /**< (SERCOM2) USART Synchronization Busy */ 78 #define REG_SERCOM2_USART_RXERRCNT (0x42000C20) /**< (SERCOM2) USART Receive Error Count */ 79 #define REG_SERCOM2_USART_DATA (0x42000C28) /**< (SERCOM2) USART Data */ 80 #define REG_SERCOM2_USART_DBGCTRL (0x42000C30) /**< (SERCOM2) USART Debug Control */ 81 82 #else 83 84 #define REG_SERCOM2_I2CM_CTRLA (*(__IO uint32_t*)0x42000C00U) /**< (SERCOM2) I2CM Control A */ 85 #define REG_SERCOM2_I2CM_CTRLB (*(__IO uint32_t*)0x42000C04U) /**< (SERCOM2) I2CM Control B */ 86 #define REG_SERCOM2_I2CM_BAUD (*(__IO uint32_t*)0x42000C0CU) /**< (SERCOM2) I2CM Baud Rate */ 87 #define REG_SERCOM2_I2CM_INTENCLR (*(__IO uint8_t*)0x42000C14U) /**< (SERCOM2) I2CM Interrupt Enable Clear */ 88 #define REG_SERCOM2_I2CM_INTENSET (*(__IO uint8_t*)0x42000C16U) /**< (SERCOM2) I2CM Interrupt Enable Set */ 89 #define REG_SERCOM2_I2CM_INTFLAG (*(__IO uint8_t*)0x42000C18U) /**< (SERCOM2) I2CM Interrupt Flag Status and Clear */ 90 #define REG_SERCOM2_I2CM_STATUS (*(__IO uint16_t*)0x42000C1AU) /**< (SERCOM2) I2CM Status */ 91 #define REG_SERCOM2_I2CM_SYNCBUSY (*(__I uint32_t*)0x42000C1CU) /**< (SERCOM2) I2CM Synchronization Busy */ 92 #define REG_SERCOM2_I2CM_ADDR (*(__IO uint32_t*)0x42000C24U) /**< (SERCOM2) I2CM Address */ 93 #define REG_SERCOM2_I2CM_DATA (*(__IO uint8_t*)0x42000C28U) /**< (SERCOM2) I2CM Data */ 94 #define REG_SERCOM2_I2CM_DBGCTRL (*(__IO uint8_t*)0x42000C30U) /**< (SERCOM2) I2CM Debug Control */ 95 #define REG_SERCOM2_I2CS_CTRLA (*(__IO uint32_t*)0x42000C00U) /**< (SERCOM2) I2CS Control A */ 96 #define REG_SERCOM2_I2CS_CTRLB (*(__IO uint32_t*)0x42000C04U) /**< (SERCOM2) I2CS Control B */ 97 #define REG_SERCOM2_I2CS_INTENCLR (*(__IO uint8_t*)0x42000C14U) /**< (SERCOM2) I2CS Interrupt Enable Clear */ 98 #define REG_SERCOM2_I2CS_INTENSET (*(__IO uint8_t*)0x42000C16U) /**< (SERCOM2) I2CS Interrupt Enable Set */ 99 #define REG_SERCOM2_I2CS_INTFLAG (*(__IO uint8_t*)0x42000C18U) /**< (SERCOM2) I2CS Interrupt Flag Status and Clear */ 100 #define REG_SERCOM2_I2CS_STATUS (*(__IO uint16_t*)0x42000C1AU) /**< (SERCOM2) I2CS Status */ 101 #define REG_SERCOM2_I2CS_SYNCBUSY (*(__I uint32_t*)0x42000C1CU) /**< (SERCOM2) I2CS Synchronization Busy */ 102 #define REG_SERCOM2_I2CS_ADDR (*(__IO uint32_t*)0x42000C24U) /**< (SERCOM2) I2CS Address */ 103 #define REG_SERCOM2_I2CS_DATA (*(__IO uint8_t*)0x42000C28U) /**< (SERCOM2) I2CS Data */ 104 #define REG_SERCOM2_SPI_CTRLA (*(__IO uint32_t*)0x42000C00U) /**< (SERCOM2) SPI Control A */ 105 #define REG_SERCOM2_SPI_CTRLB (*(__IO uint32_t*)0x42000C04U) /**< (SERCOM2) SPI Control B */ 106 #define REG_SERCOM2_SPI_BAUD (*(__IO uint8_t*)0x42000C0CU) /**< (SERCOM2) SPI Baud Rate */ 107 #define REG_SERCOM2_SPI_INTENCLR (*(__IO uint8_t*)0x42000C14U) /**< (SERCOM2) SPI Interrupt Enable Clear */ 108 #define REG_SERCOM2_SPI_INTENSET (*(__IO uint8_t*)0x42000C16U) /**< (SERCOM2) SPI Interrupt Enable Set */ 109 #define REG_SERCOM2_SPI_INTFLAG (*(__IO uint8_t*)0x42000C18U) /**< (SERCOM2) SPI Interrupt Flag Status and Clear */ 110 #define REG_SERCOM2_SPI_STATUS (*(__IO uint16_t*)0x42000C1AU) /**< (SERCOM2) SPI Status */ 111 #define REG_SERCOM2_SPI_SYNCBUSY (*(__I uint32_t*)0x42000C1CU) /**< (SERCOM2) SPI Synchronization Busy */ 112 #define REG_SERCOM2_SPI_ADDR (*(__IO uint32_t*)0x42000C24U) /**< (SERCOM2) SPI Address */ 113 #define REG_SERCOM2_SPI_DATA (*(__IO uint32_t*)0x42000C28U) /**< (SERCOM2) SPI Data */ 114 #define REG_SERCOM2_SPI_DBGCTRL (*(__IO uint8_t*)0x42000C30U) /**< (SERCOM2) SPI Debug Control */ 115 #define REG_SERCOM2_USART_CTRLA (*(__IO uint32_t*)0x42000C00U) /**< (SERCOM2) USART Control A */ 116 #define REG_SERCOM2_USART_CTRLB (*(__IO uint32_t*)0x42000C04U) /**< (SERCOM2) USART Control B */ 117 #define REG_SERCOM2_USART_CTRLC (*(__IO uint32_t*)0x42000C08U) /**< (SERCOM2) USART Control C */ 118 #define REG_SERCOM2_USART_BAUD (*(__IO uint16_t*)0x42000C0CU) /**< (SERCOM2) USART Baud Rate */ 119 #define REG_SERCOM2_USART_RXPL (*(__IO uint8_t*)0x42000C0EU) /**< (SERCOM2) USART Receive Pulse Length */ 120 #define REG_SERCOM2_USART_INTENCLR (*(__IO uint8_t*)0x42000C14U) /**< (SERCOM2) USART Interrupt Enable Clear */ 121 #define REG_SERCOM2_USART_INTENSET (*(__IO uint8_t*)0x42000C16U) /**< (SERCOM2) USART Interrupt Enable Set */ 122 #define REG_SERCOM2_USART_INTFLAG (*(__IO uint8_t*)0x42000C18U) /**< (SERCOM2) USART Interrupt Flag Status and Clear */ 123 #define REG_SERCOM2_USART_STATUS (*(__IO uint16_t*)0x42000C1AU) /**< (SERCOM2) USART Status */ 124 #define REG_SERCOM2_USART_SYNCBUSY (*(__I uint32_t*)0x42000C1CU) /**< (SERCOM2) USART Synchronization Busy */ 125 #define REG_SERCOM2_USART_RXERRCNT (*(__I uint8_t*)0x42000C20U) /**< (SERCOM2) USART Receive Error Count */ 126 #define REG_SERCOM2_USART_DATA (*(__IO uint16_t*)0x42000C28U) /**< (SERCOM2) USART Data */ 127 #define REG_SERCOM2_USART_DBGCTRL (*(__IO uint8_t*)0x42000C30U) /**< (SERCOM2) USART Debug Control */ 128 129 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 /* ========== Instance Parameter definitions for SERCOM2 peripheral ========== */ 132 #define SERCOM2_DMAC_ID_RX 8 /* Index of DMA RX trigger */ 133 #define SERCOM2_DMAC_ID_TX 9 /* Index of DMA TX trigger */ 134 #define SERCOM2_FIFO_DEPTH_POWER 1 /* Rx Fifo depth = 2^FIFO_DEPTH_POWER */ 135 #define SERCOM2_GCLK_ID_CORE 13 136 #define SERCOM2_GCLK_ID_SLOW 10 137 #define SERCOM2_INT_MSB 6 138 #define SERCOM2_PMSB 3 139 #define SERCOM2_SPI 1 /* SPI mode implemented? */ 140 #define SERCOM2_TWIM 0 /* TWI Master mode implemented? */ 141 #define SERCOM2_TWIS 0 /* TWI Slave mode implemented? */ 142 #define SERCOM2_TWI_HSMODE 0 /* TWI HighSpeed mode implemented? */ 143 #define SERCOM2_USART 1 /* USART mode implemented? */ 144 #define SERCOM2_USART_AUTOBAUD 1 /* USART AUTOBAUD mode implemented? */ 145 #define SERCOM2_USART_ISO7816 1 /* USART ISO7816 mode implemented? */ 146 #define SERCOM2_USART_LIN_MASTER 0 /* USART LIN Master mode implemented? */ 147 #define SERCOM2_USART_RS485 1 /* USART RS485 mode implemented? */ 148 #define SERCOM2_INSTANCE_ID 67 149 150 #endif /* _SAML10_SERCOM2_INSTANCE_ */ 151