1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 10 #ifndef __DM9000_H__ 11 #define __DM9000_H__ 12 13 /*MACRO DEFINATIONS*/ 14 15 16 #define SEP4020_ID_EMAC ((unsigned int) 28) // Ethernet Mac 17 /* Davicom 9161 PHY */ 18 #define MII_DM9161_ID 0x0181b880 19 #define MII_DM9161A_ID 0x0181b8a0 20 21 /* Davicom specific registers */ 22 #define MII_DSCR_REG 16 23 #define MII_DSCSR_REG 17 24 #define MII_DSINTR_REG 21 25 26 /* Intel LXT971A PHY */ 27 #define MII_LXT971A_ID 0x001378E0 28 29 /* Intel specific registers */ 30 #define MII_ISINTE_REG 18 31 #define MII_ISINTS_REG 19 32 #define MII_LEDCTRL_REG 20 33 34 /* Realtek RTL8201 PHY */ 35 #define MII_RTL8201_ID 0x00008200 36 37 /* Broadcom BCM5221 PHY */ 38 #define MII_BCM5221_ID 0x004061e0 39 40 /* Broadcom specific registers */ 41 #define MII_BCMINTR_REG 26 42 43 /* National Semiconductor DP83847 */ 44 #define MII_DP83847_ID 0x20005c30 45 46 /* Altima AC101L PHY */ 47 #define MII_AC101L_ID 0x00225520 48 49 /* Micrel KS8721 PHY */ 50 #define MII_KS8721_ID 0x00221610 51 52 /* ........................................................................ */ 53 54 #define MAX_RBUFF_SZ 0x600 /* 1518 rounded up */ 55 #define MAX_RX_DESCR 20 /* max number of receive buffers */ 56 57 #define MAX_TBUFF_SZ 0x600 /* 1518 rounded up */ 58 #define MAX_TX_DESCR 20 /* max number of receive buffers */ 59 60 #define EMAC_DESC_DONE 0x00000001 /* bit for if DMA is done */ 61 #define EMAC_DESC_WRAP 0x00000002 /* bit for wrap */ 62 63 #define EMAC_BROADCAST 0x80000000 /* broadcast address */ 64 #define EMAC_MULTICAST 0x40000000 /* multicast address */ 65 #define EMAC_UNICAST 0x20000000 /* unicast address */ 66 67 #define DM9161_inb(r) (*(volatile rt_uint8_t *)r) 68 #define DM9161_outb(r, d) (*(volatile rt_uint8_t *)r = d) 69 #define DM9161_inw(r) (*(volatile rt_uint16_t *)r) 70 #define DM9161_outw(r, d) (*(volatile rt_uint16_t *)r = d) 71 72 void rt_hw_dm9616_init(void); 73 74 #endif 75