1 /**************************************************************************//**
2 * @file core_cm0plus.h
3 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4 * @version V3.20
5 * @date 25. February 2013
6 *
7 * @note
8 *
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38 #if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #ifndef __CORE_CM0PLUS_H_GENERIC
47 #define __CORE_CM0PLUS_H_GENERIC
48
49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63 /*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66 /** \ingroup Cortex-M0+
67 @{
68 */
69
70 /* CMSIS CM0P definitions */
71 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72 #define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
74 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
75
76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
77
78
79 #if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84 #elif defined ( __ICCARM__ )
85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
87 #define __STATIC_INLINE static inline
88
89 #elif defined ( __GNUC__ )
90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
92 #define __STATIC_INLINE static inline
93
94 #elif defined ( __TASKING__ )
95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
97 #define __STATIC_INLINE static inline
98
99 #endif
100
101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
102 */
103 #define __FPU_USED 0
104
105 #if defined ( __CC_ARM )
106 #if defined __TARGET_FPU_VFP
107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #endif
109
110 #elif defined ( __ICCARM__ )
111 #if defined __ARMVFP__
112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113 #endif
114
115 #elif defined ( __GNUC__ )
116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120 #elif defined ( __TASKING__ )
121 #if defined __FPU_VFP__
122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124 #endif
125
126 #include <stdint.h> /* standard types definitions */
127 #include <core_cmInstr.h> /* Core Instruction Access */
128 #include <core_cmFunc.h> /* Core Function Access */
129
130 #endif /* __CORE_CM0PLUS_H_GENERIC */
131
132 #ifndef __CMSIS_GENERIC
133
134 #ifndef __CORE_CM0PLUS_H_DEPENDANT
135 #define __CORE_CM0PLUS_H_DEPENDANT
136
137 /* check device defines and use defaults */
138 #if defined __CHECK_DEVICE_DEFINES
139 #ifndef __CM0PLUS_REV
140 #define __CM0PLUS_REV 0x0000
141 #warning "__CM0PLUS_REV not defined in device header file; using default!"
142 #endif
143
144 #ifndef __MPU_PRESENT
145 #define __MPU_PRESENT 0
146 #warning "__MPU_PRESENT not defined in device header file; using default!"
147 #endif
148
149 #ifndef __VTOR_PRESENT
150 #define __VTOR_PRESENT 0
151 #warning "__VTOR_PRESENT not defined in device header file; using default!"
152 #endif
153
154 #ifndef __NVIC_PRIO_BITS
155 #define __NVIC_PRIO_BITS 2
156 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
157 #endif
158
159 #ifndef __Vendor_SysTickConfig
160 #define __Vendor_SysTickConfig 0
161 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
162 #endif
163 #endif
164
165 /* IO definitions (access restrictions to peripheral registers) */
166 /**
167 \defgroup CMSIS_glob_defs CMSIS Global Defines
168
169 <strong>IO Type Qualifiers</strong> are used
170 \li to specify the access to peripheral variables.
171 \li for automatic generation of peripheral register debug information.
172 */
173 #ifdef __cplusplus
174 #define __I volatile /*!< Defines 'read only' permissions */
175 #else
176 #define __I volatile const /*!< Defines 'read only' permissions */
177 #endif
178 #define __O volatile /*!< Defines 'write only' permissions */
179 #define __IO volatile /*!< Defines 'read / write' permissions */
180
181 /*@} end of group Cortex-M0+ */
182
183
184
185 /*******************************************************************************
186 * Register Abstraction
187 Core Register contain:
188 - Core Register
189 - Core NVIC Register
190 - Core SCB Register
191 - Core SysTick Register
192 - Core MPU Register
193 ******************************************************************************/
194 /** \defgroup CMSIS_core_register Defines and Type Definitions
195 \brief Type definitions and defines for Cortex-M processor based devices.
196 */
197
198 /** \ingroup CMSIS_core_register
199 \defgroup CMSIS_CORE Status and Control Registers
200 \brief Core Register type definitions.
201 @{
202 */
203
204 /** \brief Union type to access the Application Program Status Register (APSR).
205 */
206 typedef union {
207 struct {
208 #if (__CORTEX_M != 0x04)
209 uint32_t _reserved0: 27; /*!< bit: 0..26 Reserved */
210 #else
211 uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */
212 uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
213 uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */
214 #endif
215 uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
216 uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
217 uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
218 uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
219 uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
220 } b; /*!< Structure used for bit access */
221 uint32_t w; /*!< Type used for word access */
222 } APSR_Type;
223
224
225 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
226 */
227 typedef union {
228 struct {
229 uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
230 uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
231 } b; /*!< Structure used for bit access */
232 uint32_t w; /*!< Type used for word access */
233 } IPSR_Type;
234
235
236 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
237 */
238 typedef union {
239 struct {
240 uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
241 #if (__CORTEX_M != 0x04)
242 uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
243 #else
244 uint32_t _reserved0: 7; /*!< bit: 9..15 Reserved */
245 uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */
246 uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */
247 #endif
248 uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
249 uint32_t IT: 2; /*!< bit: 25..26 saved IT state (read 0) */
250 uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */
251 uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
252 uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
253 uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
254 uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
255 } b; /*!< Structure used for bit access */
256 uint32_t w; /*!< Type used for word access */
257 } xPSR_Type;
258
259
260 /** \brief Union type to access the Control Registers (CONTROL).
261 */
262 typedef union {
263 struct {
264 uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */
265 uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
266 uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */
267 uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */
268 } b; /*!< Structure used for bit access */
269 uint32_t w; /*!< Type used for word access */
270 } CONTROL_Type;
271
272 /*@} end of group CMSIS_CORE */
273
274
275 /** \ingroup CMSIS_core_register
276 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
277 \brief Type definitions for the NVIC Registers
278 @{
279 */
280
281 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
282 */
283 typedef struct {
284 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
285 uint32_t RESERVED0[31];
286 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
287 uint32_t RSERVED1[31];
288 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
289 uint32_t RESERVED2[31];
290 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
291 uint32_t RESERVED3[31];
292 uint32_t RESERVED4[64];
293 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
294 } NVIC_Type;
295
296 /*@} end of group CMSIS_NVIC */
297
298
299 /** \ingroup CMSIS_core_register
300 \defgroup CMSIS_SCB System Control Block (SCB)
301 \brief Type definitions for the System Control Block Registers
302 @{
303 */
304
305 /** \brief Structure type to access the System Control Block (SCB).
306 */
307 typedef struct {
308 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
309 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
310 #if (__VTOR_PRESENT == 1)
311 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
312 #else
313 uint32_t RESERVED0;
314 #endif
315 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
316 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
317 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
318 uint32_t RESERVED1;
319 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
320 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
321 } SCB_Type;
322
323 /* SCB CPUID Register Definitions */
324 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
325 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
326
327 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
328 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
329
330 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
331 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
332
333 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
334 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
335
336 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
337 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
338
339 /* SCB Interrupt Control State Register Definitions */
340 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
341 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
342
343 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
344 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
345
346 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
347 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
348
349 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
350 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
351
352 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
353 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
354
355 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
356 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
357
358 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
359 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
360
361 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
362 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
363
364 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
365 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
366
367 #if (__VTOR_PRESENT == 1)
368 /* SCB Interrupt Control State Register Definitions */
369 #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
370 #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
371 #endif
372
373 /* SCB Application Interrupt and Reset Control Register Definitions */
374 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
375 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
376
377 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
378 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
379
380 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
381 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
382
383 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
384 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
385
386 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
387 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
388
389 /* SCB System Control Register Definitions */
390 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
391 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
392
393 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
394 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
395
396 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
397 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
398
399 /* SCB Configuration Control Register Definitions */
400 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
401 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
402
403 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
404 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
405
406 /* SCB System Handler Control and State Register Definitions */
407 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
408 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
409
410 /*@} end of group CMSIS_SCB */
411
412
413 /** \ingroup CMSIS_core_register
414 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
415 \brief Type definitions for the System Timer Registers.
416 @{
417 */
418
419 /** \brief Structure type to access the System Timer (SysTick).
420 */
421 typedef struct {
422 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
423 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
424 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
425 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
426 } SysTick_Type;
427
428 /* SysTick Control / Status Register Definitions */
429 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
430 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
431
432 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
433 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
434
435 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
436 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
437
438 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
439 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
440
441 /* SysTick Reload Register Definitions */
442 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
443 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
444
445 /* SysTick Current Register Definitions */
446 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
447 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
448
449 /* SysTick Calibration Register Definitions */
450 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
451 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
452
453 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
454 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
455
456 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
457 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
458
459 /*@} end of group CMSIS_SysTick */
460
461 #if (__MPU_PRESENT == 1)
462 /** \ingroup CMSIS_core_register
463 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
464 \brief Type definitions for the Memory Protection Unit (MPU)
465 @{
466 */
467
468 /** \brief Structure type to access the Memory Protection Unit (MPU).
469 */
470 typedef struct {
471 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
472 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
473 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
474 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
475 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
476 } MPU_Type;
477
478 /* MPU Type Register */
479 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
480 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
481
482 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
483 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
484
485 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
486 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
487
488 /* MPU Control Register */
489 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
490 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
491
492 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
493 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
494
495 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
496 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
497
498 /* MPU Region Number Register */
499 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
500 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
501
502 /* MPU Region Base Address Register */
503 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
504 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
505
506 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
507 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
508
509 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
510 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
511
512 /* MPU Region Attribute and Size Register */
513 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
514 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
515
516 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
517 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
518
519 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
520 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
521
522 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
523 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
524
525 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
526 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
527
528 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
529 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
530
531 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
532 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
533
534 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
535 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
536
537 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
538 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
539
540 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
541 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
542
543 /*@} end of group CMSIS_MPU */
544 #endif
545
546
547 /** \ingroup CMSIS_core_register
548 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
549 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
550 are only accessible over DAP and not via processor. Therefore
551 they are not covered by the Cortex-M0 header file.
552 @{
553 */
554 /*@} end of group CMSIS_CoreDebug */
555
556
557 /** \ingroup CMSIS_core_register
558 \defgroup CMSIS_core_base Core Definitions
559 \brief Definitions for base addresses, unions, and structures.
560 @{
561 */
562
563 /* Memory mapping of Cortex-M0+ Hardware */
564 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
565 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
566 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
567 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
568
569 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
570 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
571 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
572
573 #if (__MPU_PRESENT == 1)
574 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
575 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
576 #endif
577
578 /*@} */
579
580
581
582 /*******************************************************************************
583 * Hardware Abstraction Layer
584 Core Function Interface contains:
585 - Core NVIC Functions
586 - Core SysTick Functions
587 - Core Register Access Functions
588 ******************************************************************************/
589 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
590 */
591
592
593
594 /* ########################## NVIC functions #################################### */
595 /** \ingroup CMSIS_Core_FunctionInterface
596 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
597 \brief Functions that manage interrupts and exceptions via the NVIC.
598 @{
599 */
600
601 /* Interrupt Priorities are WORD accessible only under ARMv6M */
602 /* The following MACROS handle generation of the register offset and byte masks */
603 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
604 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
605 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
606
607
608 /** \brief Enable External Interrupt
609
610 The function enables a device-specific interrupt in the NVIC interrupt controller.
611
612 \param [in] IRQn External interrupt number. Value cannot be negative.
613 */
NVIC_EnableIRQ(IRQn_Type IRQn)614 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
615 {
616 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
617 }
618
619
620 /** \brief Disable External Interrupt
621
622 The function disables a device-specific interrupt in the NVIC interrupt controller.
623
624 \param [in] IRQn External interrupt number. Value cannot be negative.
625 */
NVIC_DisableIRQ(IRQn_Type IRQn)626 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
627 {
628 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
629 }
630
631
632 /** \brief Get Pending Interrupt
633
634 The function reads the pending register in the NVIC and returns the pending bit
635 for the specified interrupt.
636
637 \param [in] IRQn Interrupt number.
638
639 \return 0 Interrupt status is not pending.
640 \return 1 Interrupt status is pending.
641 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)642 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
643 {
644 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F))) ? 1 : 0));
645 }
646
647
648 /** \brief Set Pending Interrupt
649
650 The function sets the pending bit of an external interrupt.
651
652 \param [in] IRQn Interrupt number. Value cannot be negative.
653 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)654 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
655 {
656 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
657 }
658
659
660 /** \brief Clear Pending Interrupt
661
662 The function clears the pending bit of an external interrupt.
663
664 \param [in] IRQn External interrupt number. Value cannot be negative.
665 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)666 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
667 {
668 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
669 }
670
671
672 /** \brief Set Interrupt Priority
673
674 The function sets the priority of an interrupt.
675
676 \note The priority cannot be set for every core interrupt.
677
678 \param [in] IRQn Interrupt number.
679 \param [in] priority Priority to set.
680 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)681 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
682 {
683 if(IRQn < 0) {
684 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
685 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
686 }
687 else {
688 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
689 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
690 }
691 }
692
693
694 /** \brief Get Interrupt Priority
695
696 The function reads the priority of an interrupt. The interrupt
697 number can be positive to specify an external (device specific)
698 interrupt, or negative to specify an internal (core) interrupt.
699
700
701 \param [in] IRQn Interrupt number.
702 \return Interrupt Priority. Value is aligned automatically to the implemented
703 priority bits of the microcontroller.
704 */
NVIC_GetPriority(IRQn_Type IRQn)705 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
706 {
707
708 if(IRQn < 0) {
709 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
710 } /* get priority for Cortex-M0 system interrupts */
711 else {
712 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
713 } /* get priority for device specific interrupts */
714 }
715
716
717 /** \brief System Reset
718
719 The function initiates a system reset request to reset the MCU.
720 */
NVIC_SystemReset(void)721 __STATIC_INLINE void NVIC_SystemReset(void)
722 {
723 __DSB(); /* Ensure all outstanding memory accesses included
724 buffered write are completed before reset */
725 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
726 SCB_AIRCR_SYSRESETREQ_Msk);
727 __DSB(); /* Ensure completion of memory access */
728 while(1); /* wait until reset */
729 }
730
731 /*@} end of CMSIS_Core_NVICFunctions */
732
733
734
735 /* ################################## SysTick function ############################################ */
736 /** \ingroup CMSIS_Core_FunctionInterface
737 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
738 \brief Functions that configure the System.
739 @{
740 */
741
742 #if (__Vendor_SysTickConfig == 0)
743
744 /** \brief System Tick Configuration
745
746 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
747 Counter is in free running mode to generate periodic interrupts.
748
749 \param [in] ticks Number of ticks between two interrupts.
750
751 \return 0 Function succeeded.
752 \return 1 Function failed.
753
754 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
755 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
756 must contain a vendor-specific implementation of this function.
757
758 */
SysTick_Config(uint32_t ticks)759 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
760 {
761 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
762
763 SysTick->LOAD = ticks - 1; /* set reload register */
764 NVIC_SetPriority (SysTick_IRQn, (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
765 SysTick->VAL = 0; /* Load the SysTick Counter Value */
766 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
767 SysTick_CTRL_TICKINT_Msk |
768 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
769 return (0); /* Function successful */
770 }
771
772 #endif
773
774 /*@} end of CMSIS_Core_SysTickFunctions */
775
776
777
778
779 #endif /* __CORE_CM0PLUS_H_DEPENDANT */
780
781 #endif /* __CMSIS_GENERIC */
782
783 #ifdef __cplusplus
784 }
785 #endif
786