1 /**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V5.0.1
5 * @date 25. November 2016
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_SC000_H_GENERIC
32 #define __CORE_SC000_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup SC000
60 @{
61 */
62
63 /* CMSIS SC000 definitions */
64 #define __SC000_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65 #define __SC000_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
67 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69 #define __CORTEX_SC (000U) /*!< Cortex secure core */
70
71 /** __FPU_USED indicates whether an FPU is used or not.
72 This core does not support an FPU at all
73 */
74 #define __FPU_USED 0U
75
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #endif
80
81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
82 #if defined __ARM_PCS_VFP
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #endif
85
86 #elif defined ( __GNUC__ )
87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89 #endif
90
91 #elif defined ( __ICCARM__ )
92 #if defined __ARMVFP__
93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #endif
95
96 #elif defined ( __TI_ARM__ )
97 #if defined __TI_VFP_SUPPORT__
98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99 #endif
100
101 #elif defined ( __TASKING__ )
102 #if defined __FPU_VFP__
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #endif
105
106 #elif defined ( __CSMC__ )
107 #if ( __CSMC__ & 0x400U)
108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109 #endif
110
111 #endif
112
113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
114
115
116 #ifdef __cplusplus
117 }
118 #endif
119
120 #endif /* __CORE_SC000_H_GENERIC */
121
122 #ifndef __CMSIS_GENERIC
123
124 #ifndef __CORE_SC000_H_DEPENDANT
125 #define __CORE_SC000_H_DEPENDANT
126
127 #ifdef __cplusplus
128 extern "C" {
129 #endif
130
131 /* check device defines and use defaults */
132 #if defined __CHECK_DEVICE_DEFINES
133 #ifndef __SC000_REV
134 #define __SC000_REV 0x0000U
135 #warning "__SC000_REV not defined in device header file; using default!"
136 #endif
137
138 #ifndef __MPU_PRESENT
139 #define __MPU_PRESENT 0U
140 #warning "__MPU_PRESENT not defined in device header file; using default!"
141 #endif
142
143 #ifndef __NVIC_PRIO_BITS
144 #define __NVIC_PRIO_BITS 2U
145 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
146 #endif
147
148 #ifndef __Vendor_SysTickConfig
149 #define __Vendor_SysTickConfig 0U
150 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
151 #endif
152 #endif
153
154 /* IO definitions (access restrictions to peripheral registers) */
155 /**
156 \defgroup CMSIS_glob_defs CMSIS Global Defines
157
158 <strong>IO Type Qualifiers</strong> are used
159 \li to specify the access to peripheral variables.
160 \li for automatic generation of peripheral register debug information.
161 */
162 #ifdef __cplusplus
163 #define __I volatile /*!< Defines 'read only' permissions */
164 #else
165 #define __I volatile const /*!< Defines 'read only' permissions */
166 #endif
167 #define __O volatile /*!< Defines 'write only' permissions */
168 #define __IO volatile /*!< Defines 'read / write' permissions */
169
170 /* following defines should be used for structure members */
171 #define __IM volatile const /*! Defines 'read only' structure member permissions */
172 #define __OM volatile /*! Defines 'write only' structure member permissions */
173 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
174
175 /*@} end of group SC000 */
176
177
178
179 /*******************************************************************************
180 * Register Abstraction
181 Core Register contain:
182 - Core Register
183 - Core NVIC Register
184 - Core SCB Register
185 - Core SysTick Register
186 - Core MPU Register
187 ******************************************************************************/
188 /**
189 \defgroup CMSIS_core_register Defines and Type Definitions
190 \brief Type definitions and defines for Cortex-M processor based devices.
191 */
192
193 /**
194 \ingroup CMSIS_core_register
195 \defgroup CMSIS_CORE Status and Control Registers
196 \brief Core Register type definitions.
197 @{
198 */
199
200 /**
201 \brief Union type to access the Application Program Status Register (APSR).
202 */
203 typedef union {
204 struct {
205 uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
206 uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
207 uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
208 uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
209 uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
210 } b; /*!< Structure used for bit access */
211 uint32_t w; /*!< Type used for word access */
212 } APSR_Type;
213
214 /* APSR Register Definitions */
215 #define APSR_N_Pos 31U /*!< APSR: N Position */
216 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
217
218 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
219 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
220
221 #define APSR_C_Pos 29U /*!< APSR: C Position */
222 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
223
224 #define APSR_V_Pos 28U /*!< APSR: V Position */
225 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
226
227
228 /**
229 \brief Union type to access the Interrupt Program Status Register (IPSR).
230 */
231 typedef union {
232 struct {
233 uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
234 uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
235 } b; /*!< Structure used for bit access */
236 uint32_t w; /*!< Type used for word access */
237 } IPSR_Type;
238
239 /* IPSR Register Definitions */
240 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
241 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
242
243
244 /**
245 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
246 */
247 typedef union {
248 struct {
249 uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
250 uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
251 uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
252 uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
253 uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
254 uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
255 uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
256 uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
257 } b; /*!< Structure used for bit access */
258 uint32_t w; /*!< Type used for word access */
259 } xPSR_Type;
260
261 /* xPSR Register Definitions */
262 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
263 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
264
265 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
266 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
267
268 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
269 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
270
271 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
272 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
273
274 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
275 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
276
277 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
278 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
279
280
281 /**
282 \brief Union type to access the Control Registers (CONTROL).
283 */
284 typedef union {
285 struct {
286 uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
287 uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
288 uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
289 } b; /*!< Structure used for bit access */
290 uint32_t w; /*!< Type used for word access */
291 } CONTROL_Type;
292
293 /* CONTROL Register Definitions */
294 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
295 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
296
297 /*@} end of group CMSIS_CORE */
298
299
300 /**
301 \ingroup CMSIS_core_register
302 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
303 \brief Type definitions for the NVIC Registers
304 @{
305 */
306
307 /**
308 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
309 */
310 typedef struct {
311 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
312 uint32_t RESERVED0[31U];
313 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
314 uint32_t RSERVED1[31U];
315 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
316 uint32_t RESERVED2[31U];
317 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
318 uint32_t RESERVED3[31U];
319 uint32_t RESERVED4[64U];
320 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
321 } NVIC_Type;
322
323 /*@} end of group CMSIS_NVIC */
324
325
326 /**
327 \ingroup CMSIS_core_register
328 \defgroup CMSIS_SCB System Control Block (SCB)
329 \brief Type definitions for the System Control Block Registers
330 @{
331 */
332
333 /**
334 \brief Structure type to access the System Control Block (SCB).
335 */
336 typedef struct {
337 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
338 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
339 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
340 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
341 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
342 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
343 uint32_t RESERVED0[1U];
344 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
345 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
346 uint32_t RESERVED1[154U];
347 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
348 } SCB_Type;
349
350 /* SCB CPUID Register Definitions */
351 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
352 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
353
354 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
355 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
356
357 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
358 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
359
360 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
361 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
362
363 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
364 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
365
366 /* SCB Interrupt Control State Register Definitions */
367 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
368 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
369
370 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
371 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
372
373 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
374 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
375
376 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
377 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
378
379 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
380 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
381
382 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
383 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
384
385 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
386 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
387
388 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
389 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
390
391 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
392 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
393
394 /* SCB Interrupt Control State Register Definitions */
395 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
396 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
397
398 /* SCB Application Interrupt and Reset Control Register Definitions */
399 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
400 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
401
402 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
403 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
404
405 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
406 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
407
408 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
410
411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
413
414 /* SCB System Control Register Definitions */
415 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
416 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
417
418 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
419 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
420
421 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
422 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
423
424 /* SCB Configuration Control Register Definitions */
425 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
426 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
427
428 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
429 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
430
431 /* SCB System Handler Control and State Register Definitions */
432 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
433 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
434
435 /*@} end of group CMSIS_SCB */
436
437
438 /**
439 \ingroup CMSIS_core_register
440 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
441 \brief Type definitions for the System Control and ID Register not in the SCB
442 @{
443 */
444
445 /**
446 \brief Structure type to access the System Control and ID Register not in the SCB.
447 */
448 typedef struct {
449 uint32_t RESERVED0[2U];
450 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
451 } SCnSCB_Type;
452
453 /* Auxiliary Control Register Definitions */
454 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
455 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
456
457 /*@} end of group CMSIS_SCnotSCB */
458
459
460 /**
461 \ingroup CMSIS_core_register
462 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
463 \brief Type definitions for the System Timer Registers.
464 @{
465 */
466
467 /**
468 \brief Structure type to access the System Timer (SysTick).
469 */
470 typedef struct {
471 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
472 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
473 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
474 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
475 } SysTick_Type;
476
477 /* SysTick Control / Status Register Definitions */
478 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
479 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
480
481 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
482 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
483
484 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
485 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
486
487 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
488 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
489
490 /* SysTick Reload Register Definitions */
491 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
492 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
493
494 /* SysTick Current Register Definitions */
495 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
496 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
497
498 /* SysTick Calibration Register Definitions */
499 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
500 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
501
502 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
503 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
504
505 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
506 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
507
508 /*@} end of group CMSIS_SysTick */
509
510 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
511 /**
512 \ingroup CMSIS_core_register
513 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
514 \brief Type definitions for the Memory Protection Unit (MPU)
515 @{
516 */
517
518 /**
519 \brief Structure type to access the Memory Protection Unit (MPU).
520 */
521 typedef struct {
522 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
523 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
524 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
525 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
526 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
527 } MPU_Type;
528
529 /* MPU Type Register Definitions */
530 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
531 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
532
533 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
534 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
535
536 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
537 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
538
539 /* MPU Control Register Definitions */
540 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
541 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
542
543 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
544 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
545
546 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
547 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
548
549 /* MPU Region Number Register Definitions */
550 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
551 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
552
553 /* MPU Region Base Address Register Definitions */
554 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
555 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
556
557 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
558 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
559
560 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
561 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
562
563 /* MPU Region Attribute and Size Register Definitions */
564 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
565 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
566
567 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
568 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
569
570 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
571 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
572
573 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
574 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
575
576 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
577 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
578
579 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
580 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
581
582 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
583 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
584
585 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
586 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
587
588 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
589 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
590
591 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
592 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
593
594 /*@} end of group CMSIS_MPU */
595 #endif
596
597
598 /**
599 \ingroup CMSIS_core_register
600 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
601 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
602 Therefore they are not covered by the SC000 header file.
603 @{
604 */
605 /*@} end of group CMSIS_CoreDebug */
606
607
608 /**
609 \ingroup CMSIS_core_register
610 \defgroup CMSIS_core_bitfield Core register bit field macros
611 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
612 @{
613 */
614
615 /**
616 \brief Mask and shift a bit field value for use in a register bit range.
617 \param[in] field Name of the register bit field.
618 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
619 \return Masked and shifted value.
620 */
621 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
622
623 /**
624 \brief Mask and shift a register value to extract a bit filed value.
625 \param[in] field Name of the register bit field.
626 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
627 \return Masked and shifted bit field value.
628 */
629 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
630
631 /*@} end of group CMSIS_core_bitfield */
632
633
634 /**
635 \ingroup CMSIS_core_register
636 \defgroup CMSIS_core_base Core Definitions
637 \brief Definitions for base addresses, unions, and structures.
638 @{
639 */
640
641 /* Memory mapping of Core Hardware */
642 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
643 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
644 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
645 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
646
647 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
648 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
649 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
650 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
651
652 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
653 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
654 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
655 #endif
656
657 /*@} */
658
659
660
661 /*******************************************************************************
662 * Hardware Abstraction Layer
663 Core Function Interface contains:
664 - Core NVIC Functions
665 - Core SysTick Functions
666 - Core Register Access Functions
667 ******************************************************************************/
668 /**
669 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
670 */
671
672
673
674 /* ########################## NVIC functions #################################### */
675 /**
676 \ingroup CMSIS_Core_FunctionInterface
677 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
678 \brief Functions that manage interrupts and exceptions via the NVIC.
679 @{
680 */
681
682 #ifndef CMSIS_NVIC_VIRTUAL
683 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
684 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
685 #define NVIC_EnableIRQ __NVIC_EnableIRQ
686 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
687 #define NVIC_DisableIRQ __NVIC_DisableIRQ
688 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
689 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
690 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
691 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
692 #define NVIC_SetPriority __NVIC_SetPriority
693 #define NVIC_GetPriority __NVIC_GetPriority
694 #endif /* CMSIS_NVIC_VIRTUAL */
695
696 #ifndef CMSIS_VECTAB_VIRTUAL
697 #define NVIC_SetVector __NVIC_SetVector
698 #define NVIC_GetVector __NVIC_GetVector
699 #endif /* (CMSIS_VECTAB_VIRTUAL) */
700
701 #define NVIC_USER_IRQ_OFFSET 16
702
703
704 /* Interrupt Priorities are WORD accessible only under ARMv6M */
705 /* The following MACROS handle generation of the register offset and byte masks */
706 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
707 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
708 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
709
710
711 /**
712 \brief Enable Interrupt
713 \details Enables a device specific interrupt in the NVIC interrupt controller.
714 \param [in] IRQn Device specific interrupt number.
715 \note IRQn must not be negative.
716 */
__NVIC_EnableIRQ(IRQn_Type IRQn)717 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
718 {
719 if ((int32_t)(IRQn) >= 0) {
720 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
721 }
722 }
723
724
725 /**
726 \brief Get Interrupt Enable status
727 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
728 \param [in] IRQn Device specific interrupt number.
729 \return 0 Interrupt is not enabled.
730 \return 1 Interrupt is enabled.
731 \note IRQn must not be negative.
732 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)733 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
734 {
735 if ((int32_t)(IRQn) >= 0) {
736 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
737 }
738 else {
739 return(0U);
740 }
741 }
742
743
744 /**
745 \brief Disable Interrupt
746 \details Disables a device specific interrupt in the NVIC interrupt controller.
747 \param [in] IRQn Device specific interrupt number.
748 \note IRQn must not be negative.
749 */
__NVIC_DisableIRQ(IRQn_Type IRQn)750 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
751 {
752 if ((int32_t)(IRQn) >= 0) {
753 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
754 __DSB();
755 __ISB();
756 }
757 }
758
759
760 /**
761 \brief Get Pending Interrupt
762 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
763 \param [in] IRQn Device specific interrupt number.
764 \return 0 Interrupt status is not pending.
765 \return 1 Interrupt status is pending.
766 \note IRQn must not be negative.
767 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)768 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
769 {
770 if ((int32_t)(IRQn) >= 0) {
771 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
772 }
773 else {
774 return(0U);
775 }
776 }
777
778
779 /**
780 \brief Set Pending Interrupt
781 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
782 \param [in] IRQn Device specific interrupt number.
783 \note IRQn must not be negative.
784 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)785 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
786 {
787 if ((int32_t)(IRQn) >= 0) {
788 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
789 }
790 }
791
792
793 /**
794 \brief Clear Pending Interrupt
795 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
796 \param [in] IRQn Device specific interrupt number.
797 \note IRQn must not be negative.
798 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)799 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
800 {
801 if ((int32_t)(IRQn) >= 0) {
802 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
803 }
804 }
805
806
807 /**
808 \brief Set Interrupt Priority
809 \details Sets the priority of a device specific interrupt or a processor exception.
810 The interrupt number can be positive to specify a device specific interrupt,
811 or negative to specify a processor exception.
812 \param [in] IRQn Interrupt number.
813 \param [in] priority Priority to set.
814 \note The priority cannot be set for every processor exception.
815 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)816 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
817 {
818 if ((int32_t)(IRQn) >= 0) {
819 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
820 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
821 }
822 else {
823 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
824 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
825 }
826 }
827
828
829 /**
830 \brief Get Interrupt Priority
831 \details Reads the priority of a device specific interrupt or a processor exception.
832 The interrupt number can be positive to specify a device specific interrupt,
833 or negative to specify a processor exception.
834 \param [in] IRQn Interrupt number.
835 \return Interrupt Priority.
836 Value is aligned automatically to the implemented priority bits of the microcontroller.
837 */
__NVIC_GetPriority(IRQn_Type IRQn)838 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
839 {
840
841 if ((int32_t)(IRQn) >= 0) {
842 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
843 }
844 else {
845 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
846 }
847 }
848
849
850 /**
851 \brief Set Interrupt Vector
852 \details Sets an interrupt vector in SRAM based interrupt vector table.
853 The interrupt number can be positive to specify a device specific interrupt,
854 or negative to specify a processor exception.
855 VTOR must been relocated to SRAM before.
856 \param [in] IRQn Interrupt number
857 \param [in] vector Address of interrupt handler function
858 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)859 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
860 {
861 uint32_t* vectors = (uint32_t*)SCB->VTOR;
862 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
863 }
864
865
866 /**
867 \brief Get Interrupt Vector
868 \details Reads an interrupt vector from interrupt vector table.
869 The interrupt number can be positive to specify a device specific interrupt,
870 or negative to specify a processor exception.
871 \param [in] IRQn Interrupt number.
872 \return Address of interrupt handler function
873 */
__NVIC_GetVector(IRQn_Type IRQn)874 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
875 {
876 uint32_t* vectors = (uint32_t*)SCB->VTOR;
877 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
878 }
879
880
881 /**
882 \brief System Reset
883 \details Initiates a system reset request to reset the MCU.
884 */
NVIC_SystemReset(void)885 __STATIC_INLINE void NVIC_SystemReset(void)
886 {
887 __DSB(); /* Ensure all outstanding memory accesses included
888 buffered write are completed before reset */
889 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
890 SCB_AIRCR_SYSRESETREQ_Msk);
891 __DSB(); /* Ensure completion of memory access */
892
893 for(;;) { /* wait until reset */
894 __NOP();
895 }
896 }
897
898 /*@} end of CMSIS_Core_NVICFunctions */
899
900
901 /* ########################## FPU functions #################################### */
902 /**
903 \ingroup CMSIS_Core_FunctionInterface
904 \defgroup CMSIS_Core_FpuFunctions FPU Functions
905 \brief Function that provides FPU type.
906 @{
907 */
908
909 /**
910 \brief get FPU type
911 \details returns the FPU type
912 \returns
913 - \b 0: No FPU
914 - \b 1: Single precision FPU
915 - \b 2: Double + Single precision FPU
916 */
SCB_GetFPUType(void)917 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
918 {
919 return 0U; /* No FPU */
920 }
921
922
923 /*@} end of CMSIS_Core_FpuFunctions */
924
925
926
927 /* ################################## SysTick function ############################################ */
928 /**
929 \ingroup CMSIS_Core_FunctionInterface
930 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
931 \brief Functions that configure the System.
932 @{
933 */
934
935 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
936
937 /**
938 \brief System Tick Configuration
939 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
940 Counter is in free running mode to generate periodic interrupts.
941 \param [in] ticks Number of ticks between two interrupts.
942 \return 0 Function succeeded.
943 \return 1 Function failed.
944 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
945 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
946 must contain a vendor-specific implementation of this function.
947 */
SysTick_Config(uint32_t ticks)948 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
949 {
950 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
951 return (1UL); /* Reload value impossible */
952 }
953
954 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
955 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
956 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
957 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
958 SysTick_CTRL_TICKINT_Msk |
959 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
960 return (0UL); /* Function successful */
961 }
962
963 #endif
964
965 /*@} end of CMSIS_Core_SysTickFunctions */
966
967
968
969
970 #ifdef __cplusplus
971 }
972 #endif
973
974 #endif /* __CORE_SC000_H_DEPENDANT */
975
976 #endif /* __CMSIS_GENERIC */
977