1 /**************************************************************************//**
2 * @file core_cm0.h
3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4 * @version V5.0.1
5 * @date 25. November 2016
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
28 #pragma clang system_header /* treat file as system include file */
29 #endif
30
31 #ifndef __CORE_CM0_H_GENERIC
32 #define __CORE_CM0_H_GENERIC
33
34 #include <stdint.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /**
41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42 CMSIS violates the following MISRA-C:2004 rules:
43
44 \li Required Rule 8.5, object/function definition in header file.<br>
45 Function definitions in header files are used to allow 'inlining'.
46
47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48 Unions are used for effective representation of core registers.
49
50 \li Advisory Rule 19.7, Function-like macro defined.<br>
51 Function-like macros are used to allow more efficient code.
52 */
53
54
55 /*******************************************************************************
56 * CMSIS definitions
57 ******************************************************************************/
58 /**
59 \ingroup Cortex_M0
60 @{
61 */
62
63 /* CMSIS CM0 definitions */
64 #define __CM0_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS HAL main version */
65 #define __CM0_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS HAL sub version */
66 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
67 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
68
69 #define __CORTEX_M (0U) /*!< Cortex-M Core */
70
71 /** __FPU_USED indicates whether an FPU is used or not.
72 This core does not support an FPU at all
73 */
74 #define __FPU_USED 0U
75
76 #if defined ( __CC_ARM )
77 #if defined __TARGET_FPU_VFP
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #endif
80
81 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
82 #if defined __ARM_PCS_VFP
83 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
84 #endif
85
86 #elif defined ( __GNUC__ )
87 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
88 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
89 #endif
90
91 #elif defined ( __ICCARM__ )
92 #if defined __ARMVFP__
93 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94 #endif
95
96 #elif defined ( __TI_ARM__ )
97 #if defined __TI_VFP_SUPPORT__
98 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
99 #endif
100
101 #elif defined ( __TASKING__ )
102 #if defined __FPU_VFP__
103 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
104 #endif
105
106 #elif defined ( __CSMC__ )
107 #if ( __CSMC__ & 0x400U)
108 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
109 #endif
110
111 #endif
112
113 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
114
115
116 #ifdef __cplusplus
117 }
118 #endif
119
120 #endif /* __CORE_CM0_H_GENERIC */
121
122 #ifndef __CMSIS_GENERIC
123
124 #ifndef __CORE_CM0_H_DEPENDANT
125 #define __CORE_CM0_H_DEPENDANT
126
127 #ifdef __cplusplus
128 extern "C" {
129 #endif
130
131 /* check device defines and use defaults */
132 #if defined __CHECK_DEVICE_DEFINES
133 #ifndef __CM0_REV
134 #define __CM0_REV 0x0000U
135 #warning "__CM0_REV not defined in device header file; using default!"
136 #endif
137
138 #ifndef __NVIC_PRIO_BITS
139 #define __NVIC_PRIO_BITS 2U
140 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
141 #endif
142
143 #ifndef __Vendor_SysTickConfig
144 #define __Vendor_SysTickConfig 0U
145 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
146 #endif
147 #endif
148
149 /* IO definitions (access restrictions to peripheral registers) */
150 /**
151 \defgroup CMSIS_glob_defs CMSIS Global Defines
152
153 <strong>IO Type Qualifiers</strong> are used
154 \li to specify the access to peripheral variables.
155 \li for automatic generation of peripheral register debug information.
156 */
157 #ifdef __cplusplus
158 #define __I volatile /*!< Defines 'read only' permissions */
159 #else
160 #define __I volatile const /*!< Defines 'read only' permissions */
161 #endif
162 #define __O volatile /*!< Defines 'write only' permissions */
163 #define __IO volatile /*!< Defines 'read / write' permissions */
164
165 /* following defines should be used for structure members */
166 #define __IM volatile const /*! Defines 'read only' structure member permissions */
167 #define __OM volatile /*! Defines 'write only' structure member permissions */
168 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
169
170 /*@} end of group Cortex_M0 */
171
172
173
174 /*******************************************************************************
175 * Register Abstraction
176 Core Register contain:
177 - Core Register
178 - Core NVIC Register
179 - Core SCB Register
180 - Core SysTick Register
181 ******************************************************************************/
182 /**
183 \defgroup CMSIS_core_register Defines and Type Definitions
184 \brief Type definitions and defines for Cortex-M processor based devices.
185 */
186
187 /**
188 \ingroup CMSIS_core_register
189 \defgroup CMSIS_CORE Status and Control Registers
190 \brief Core Register type definitions.
191 @{
192 */
193
194 /**
195 \brief Union type to access the Application Program Status Register (APSR).
196 */
197 typedef union {
198 struct {
199 uint32_t _reserved0: 28; /*!< bit: 0..27 Reserved */
200 uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
201 uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
202 uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
203 uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
204 } b; /*!< Structure used for bit access */
205 uint32_t w; /*!< Type used for word access */
206 } APSR_Type;
207
208 /* APSR Register Definitions */
209 #define APSR_N_Pos 31U /*!< APSR: N Position */
210 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
211
212 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
213 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
214
215 #define APSR_C_Pos 29U /*!< APSR: C Position */
216 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
217
218 #define APSR_V_Pos 28U /*!< APSR: V Position */
219 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
220
221
222 /**
223 \brief Union type to access the Interrupt Program Status Register (IPSR).
224 */
225 typedef union {
226 struct {
227 uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
228 uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */
229 } b; /*!< Structure used for bit access */
230 uint32_t w; /*!< Type used for word access */
231 } IPSR_Type;
232
233 /* IPSR Register Definitions */
234 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
235 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
236
237
238 /**
239 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
240 */
241 typedef union {
242 struct {
243 uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */
244 uint32_t _reserved0: 15; /*!< bit: 9..23 Reserved */
245 uint32_t T: 1; /*!< bit: 24 Thumb bit (read 0) */
246 uint32_t _reserved1: 3; /*!< bit: 25..27 Reserved */
247 uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */
248 uint32_t C: 1; /*!< bit: 29 Carry condition code flag */
249 uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */
250 uint32_t N: 1; /*!< bit: 31 Negative condition code flag */
251 } b; /*!< Structure used for bit access */
252 uint32_t w; /*!< Type used for word access */
253 } xPSR_Type;
254
255 /* xPSR Register Definitions */
256 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
257 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
258
259 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
260 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
261
262 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
263 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
264
265 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
266 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
267
268 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
269 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
270
271 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
272 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
273
274
275 /**
276 \brief Union type to access the Control Registers (CONTROL).
277 */
278 typedef union {
279 struct {
280 uint32_t _reserved0: 1; /*!< bit: 0 Reserved */
281 uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */
282 uint32_t _reserved1: 30; /*!< bit: 2..31 Reserved */
283 } b; /*!< Structure used for bit access */
284 uint32_t w; /*!< Type used for word access */
285 } CONTROL_Type;
286
287 /* CONTROL Register Definitions */
288 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
289 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
290
291 /*@} end of group CMSIS_CORE */
292
293
294 /**
295 \ingroup CMSIS_core_register
296 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
297 \brief Type definitions for the NVIC Registers
298 @{
299 */
300
301 /**
302 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
303 */
304 typedef struct {
305 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
306 uint32_t RESERVED0[31U];
307 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
308 uint32_t RSERVED1[31U];
309 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
310 uint32_t RESERVED2[31U];
311 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
312 uint32_t RESERVED3[31U];
313 uint32_t RESERVED4[64U];
314 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
315 } NVIC_Type;
316
317 /*@} end of group CMSIS_NVIC */
318
319
320 /**
321 \ingroup CMSIS_core_register
322 \defgroup CMSIS_SCB System Control Block (SCB)
323 \brief Type definitions for the System Control Block Registers
324 @{
325 */
326
327 /**
328 \brief Structure type to access the System Control Block (SCB).
329 */
330 typedef struct {
331 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
332 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
333 uint32_t RESERVED0;
334 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
335 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
336 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
337 uint32_t RESERVED1;
338 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
339 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
340 } SCB_Type;
341
342 /* SCB CPUID Register Definitions */
343 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
344 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
345
346 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
347 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
348
349 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
350 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
351
352 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
353 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
354
355 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
356 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
357
358 /* SCB Interrupt Control State Register Definitions */
359 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
360 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
361
362 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
363 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
364
365 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
366 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
367
368 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
369 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
370
371 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
372 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
373
374 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
375 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
376
377 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
378 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
379
380 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
381 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
382
383 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
384 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
385
386 /* SCB Application Interrupt and Reset Control Register Definitions */
387 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
388 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
389
390 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
391 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
392
393 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
394 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
395
396 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
397 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
398
399 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
400 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
401
402 /* SCB System Control Register Definitions */
403 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
404 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
405
406 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
407 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
408
409 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
410 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
411
412 /* SCB Configuration Control Register Definitions */
413 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
414 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
415
416 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
417 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
418
419 /* SCB System Handler Control and State Register Definitions */
420 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
421 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
422
423 /*@} end of group CMSIS_SCB */
424
425
426 /**
427 \ingroup CMSIS_core_register
428 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
429 \brief Type definitions for the System Timer Registers.
430 @{
431 */
432
433 /**
434 \brief Structure type to access the System Timer (SysTick).
435 */
436 typedef struct {
437 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
438 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
439 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
440 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
441 } SysTick_Type;
442
443 /* SysTick Control / Status Register Definitions */
444 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
445 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
446
447 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
448 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
449
450 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
451 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
452
453 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
454 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
455
456 /* SysTick Reload Register Definitions */
457 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
458 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
459
460 /* SysTick Current Register Definitions */
461 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
462 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
463
464 /* SysTick Calibration Register Definitions */
465 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
466 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
467
468 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
469 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
470
471 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
472 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
473
474 /*@} end of group CMSIS_SysTick */
475
476
477 /**
478 \ingroup CMSIS_core_register
479 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
480 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
481 Therefore they are not covered by the Cortex-M0 header file.
482 @{
483 */
484 /*@} end of group CMSIS_CoreDebug */
485
486
487 /**
488 \ingroup CMSIS_core_register
489 \defgroup CMSIS_core_bitfield Core register bit field macros
490 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
491 @{
492 */
493
494 /**
495 \brief Mask and shift a bit field value for use in a register bit range.
496 \param[in] field Name of the register bit field.
497 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
498 \return Masked and shifted value.
499 */
500 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
501
502 /**
503 \brief Mask and shift a register value to extract a bit filed value.
504 \param[in] field Name of the register bit field.
505 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
506 \return Masked and shifted bit field value.
507 */
508 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
509
510 /*@} end of group CMSIS_core_bitfield */
511
512
513 /**
514 \ingroup CMSIS_core_register
515 \defgroup CMSIS_core_base Core Definitions
516 \brief Definitions for base addresses, unions, and structures.
517 @{
518 */
519
520 /* Memory mapping of Core Hardware */
521 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
522 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
523 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
524 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
525
526 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
527 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
528 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
529
530
531 /*@} */
532
533
534
535 /*******************************************************************************
536 * Hardware Abstraction Layer
537 Core Function Interface contains:
538 - Core NVIC Functions
539 - Core SysTick Functions
540 - Core Register Access Functions
541 ******************************************************************************/
542 /**
543 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
544 */
545
546
547
548 /* ########################## NVIC functions #################################### */
549 /**
550 \ingroup CMSIS_Core_FunctionInterface
551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
552 \brief Functions that manage interrupts and exceptions via the NVIC.
553 @{
554 */
555
556 #ifndef CMSIS_NVIC_VIRTUAL
557 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
558 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
559 #define NVIC_EnableIRQ __NVIC_EnableIRQ
560 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
561 #define NVIC_DisableIRQ __NVIC_DisableIRQ
562 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
563 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
564 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
565 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
566 #define NVIC_SetPriority __NVIC_SetPriority
567 #define NVIC_GetPriority __NVIC_GetPriority
568 #endif /* CMSIS_NVIC_VIRTUAL */
569
570 #ifndef CMSIS_VECTAB_VIRTUAL
571 #define NVIC_SetVector __NVIC_SetVector
572 #define NVIC_GetVector __NVIC_GetVector
573 #endif /* (CMSIS_VECTAB_VIRTUAL) */
574
575 #define NVIC_USER_IRQ_OFFSET 16
576
577
578 /* Interrupt Priorities are WORD accessible only under ARMv6M */
579 /* The following MACROS handle generation of the register offset and byte masks */
580 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
581 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
582 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
583
584
585 /**
586 \brief Enable Interrupt
587 \details Enables a device specific interrupt in the NVIC interrupt controller.
588 \param [in] IRQn Device specific interrupt number.
589 \note IRQn must not be negative.
590 */
__NVIC_EnableIRQ(IRQn_Type IRQn)591 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
592 {
593 if ((int32_t)(IRQn) >= 0) {
594 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
595 }
596 }
597
598
599 /**
600 \brief Get Interrupt Enable status
601 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
602 \param [in] IRQn Device specific interrupt number.
603 \return 0 Interrupt is not enabled.
604 \return 1 Interrupt is enabled.
605 \note IRQn must not be negative.
606 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)607 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
608 {
609 if ((int32_t)(IRQn) >= 0) {
610 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
611 }
612 else {
613 return(0U);
614 }
615 }
616
617
618 /**
619 \brief Disable Interrupt
620 \details Disables a device specific interrupt in the NVIC interrupt controller.
621 \param [in] IRQn Device specific interrupt number.
622 \note IRQn must not be negative.
623 */
__NVIC_DisableIRQ(IRQn_Type IRQn)624 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
625 {
626 if ((int32_t)(IRQn) >= 0) {
627 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
628 __DSB();
629 __ISB();
630 }
631 }
632
633
634 /**
635 \brief Get Pending Interrupt
636 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
637 \param [in] IRQn Device specific interrupt number.
638 \return 0 Interrupt status is not pending.
639 \return 1 Interrupt status is pending.
640 \note IRQn must not be negative.
641 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)642 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
643 {
644 if ((int32_t)(IRQn) >= 0) {
645 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
646 }
647 else {
648 return(0U);
649 }
650 }
651
652
653 /**
654 \brief Set Pending Interrupt
655 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
656 \param [in] IRQn Device specific interrupt number.
657 \note IRQn must not be negative.
658 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)659 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
660 {
661 if ((int32_t)(IRQn) >= 0) {
662 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
663 }
664 }
665
666
667 /**
668 \brief Clear Pending Interrupt
669 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
670 \param [in] IRQn Device specific interrupt number.
671 \note IRQn must not be negative.
672 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)673 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
674 {
675 if ((int32_t)(IRQn) >= 0) {
676 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
677 }
678 }
679
680
681 /**
682 \brief Set Interrupt Priority
683 \details Sets the priority of a device specific interrupt or a processor exception.
684 The interrupt number can be positive to specify a device specific interrupt,
685 or negative to specify a processor exception.
686 \param [in] IRQn Interrupt number.
687 \param [in] priority Priority to set.
688 \note The priority cannot be set for every processor exception.
689 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)690 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
691 {
692 if ((int32_t)(IRQn) >= 0) {
693 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
694 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
695 }
696 else {
697 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
698 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
699 }
700 }
701
702
703 /**
704 \brief Get Interrupt Priority
705 \details Reads the priority of a device specific interrupt or a processor exception.
706 The interrupt number can be positive to specify a device specific interrupt,
707 or negative to specify a processor exception.
708 \param [in] IRQn Interrupt number.
709 \return Interrupt Priority.
710 Value is aligned automatically to the implemented priority bits of the microcontroller.
711 */
__NVIC_GetPriority(IRQn_Type IRQn)712 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
713 {
714
715 if ((int32_t)(IRQn) >= 0) {
716 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
717 }
718 else {
719 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
720 }
721 }
722
723
724 /**
725 \brief Set Interrupt Vector
726 \details Sets an interrupt vector in SRAM based interrupt vector table.
727 The interrupt number can be positive to specify a device specific interrupt,
728 or negative to specify a processor exception.
729 Address 0 must be mapped to SRAM.
730 \param [in] IRQn Interrupt number
731 \param [in] vector Address of interrupt handler function
732 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)733 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
734 {
735 uint32_t* vectors = (uint32_t*)0x0U;
736 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
737 }
738
739
740 /**
741 \brief Get Interrupt Vector
742 \details Reads an interrupt vector from interrupt vector table.
743 The interrupt number can be positive to specify a device specific interrupt,
744 or negative to specify a processor exception.
745 \param [in] IRQn Interrupt number.
746 \return Address of interrupt handler function
747 */
__NVIC_GetVector(IRQn_Type IRQn)748 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
749 {
750 uint32_t* vectors = (uint32_t*)0x0U;
751 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
752 }
753
754
755 /**
756 \brief System Reset
757 \details Initiates a system reset request to reset the MCU.
758 */
NVIC_SystemReset(void)759 __STATIC_INLINE void NVIC_SystemReset(void)
760 {
761 __DSB(); /* Ensure all outstanding memory accesses included
762 buffered write are completed before reset */
763 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
764 SCB_AIRCR_SYSRESETREQ_Msk);
765 __DSB(); /* Ensure completion of memory access */
766
767 for(;;) { /* wait until reset */
768 __NOP();
769 }
770 }
771
772 /*@} end of CMSIS_Core_NVICFunctions */
773
774
775 /* ########################## FPU functions #################################### */
776 /**
777 \ingroup CMSIS_Core_FunctionInterface
778 \defgroup CMSIS_Core_FpuFunctions FPU Functions
779 \brief Function that provides FPU type.
780 @{
781 */
782
783 /**
784 \brief get FPU type
785 \details returns the FPU type
786 \returns
787 - \b 0: No FPU
788 - \b 1: Single precision FPU
789 - \b 2: Double + Single precision FPU
790 */
SCB_GetFPUType(void)791 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
792 {
793 return 0U; /* No FPU */
794 }
795
796
797 /*@} end of CMSIS_Core_FpuFunctions */
798
799
800
801 /* ################################## SysTick function ############################################ */
802 /**
803 \ingroup CMSIS_Core_FunctionInterface
804 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
805 \brief Functions that configure the System.
806 @{
807 */
808
809 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
810
811 /**
812 \brief System Tick Configuration
813 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
814 Counter is in free running mode to generate periodic interrupts.
815 \param [in] ticks Number of ticks between two interrupts.
816 \return 0 Function succeeded.
817 \return 1 Function failed.
818 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
819 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
820 must contain a vendor-specific implementation of this function.
821 */
SysTick_Config(uint32_t ticks)822 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
823 {
824 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {
825 return (1UL); /* Reload value impossible */
826 }
827
828 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
829 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
830 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
831 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
832 SysTick_CTRL_TICKINT_Msk |
833 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
834 return (0UL); /* Function successful */
835 }
836
837 #endif
838
839 /*@} end of CMSIS_Core_SysTickFunctions */
840
841
842
843
844 #ifdef __cplusplus
845 }
846 #endif
847
848 #endif /* __CORE_CM0_H_DEPENDANT */
849
850 #endif /* __CMSIS_GENERIC */
851