1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file hal_dma.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE DMA 5 /// FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 #ifndef __HAL_DMA_H 21 #define __HAL_DMA_H 22 // Files includes 23 #include "types.h" 24 #include "reg_common.h" 25 #include "reg_dma.h" 26 27 //////////////////////////////////////////////////////////////////////////////// 28 /// @addtogroup MM32_Hardware_Abstract_Layer 29 /// @{ 30 31 //////////////////////////////////////////////////////////////////////////////// 32 /// @defgroup DMA_HAL 33 /// @brief DMA HAL modules 34 /// @{ 35 36 //////////////////////////////////////////////////////////////////////////////// 37 /// @defgroup DMA_Exported_Types 38 /// @{ 39 40 //////////////////////////////////////////////////////////////////////////////// 41 /// @brief DMA data transfer direction Enumerate definition 42 /// @anchor DMA_data_transfer_direction 43 //////////////////////////////////////////////////////////////////////////////// 44 typedef enum { 45 DMA_DIR_PeripheralSRC = 0U, 46 DMA_DIR_PeripheralDST = DMA_CCR_DIR // 0x00000010U 47 } DMA_data_transfer_direction_TypeDef; 48 49 //////////////////////////////////////////////////////////////////////////////// 50 /// @brief DMA peripheral incremented mode Enumerate definition 51 /// @anchor DMA_peripheral_incremented_mode 52 //////////////////////////////////////////////////////////////////////////////// 53 typedef enum { 54 DMA_PeripheralInc_Disable = 0U, 55 DMA_PeripheralInc_Enable = DMA_CCR_PINC // 0x00000040U 56 } DMA_peripheral_incremented_mode_TypeDef; 57 58 //////////////////////////////////////////////////////////////////////////////// 59 /// @brief DMA memory incremented mode Enumerate definition 60 /// @anchor DMA_memory_incremented_mode 61 //////////////////////////////////////////////////////////////////////////////// 62 typedef enum { 63 DMA_MemoryInc_Disable = 0U, 64 DMA_MemoryInc_Enable = DMA_CCR_MINC // 0x00000080U 65 } DMA_memory_incremented_mode_TypeDef; 66 67 //////////////////////////////////////////////////////////////////////////////// 68 /// @brief DMA peripheral data size Enumerate definition 69 /// @anchor DMA_peripheral_data_size 70 //////////////////////////////////////////////////////////////////////////////// 71 typedef enum { 72 DMA_PeripheralDataSize_Byte = 0U, 73 DMA_PeripheralDataSize_HalfWord = DMA_CCR_PSIZE_HALFWORD, 74 DMA_PeripheralDataSize_Word = DMA_CCR_PSIZE_WORD 75 } DMA_peripheral_data_size_TypeDef; 76 77 //////////////////////////////////////////////////////////////////////////////// 78 /// @brief DMA memory data size Enumerate definition 79 /// @anchor DMA_memory_data_size 80 //////////////////////////////////////////////////////////////////////////////// 81 typedef enum { 82 DMA_MemoryDataSize_Byte = 0U, 83 DMA_MemoryDataSize_HalfWord = DMA_CCR_MSIZE_HALFWORD, // 0x00000400U 84 DMA_MemoryDataSize_Word = DMA_CCR_MSIZE_WORD // 0x00000800U 85 } DMA_memory_data_size_TypeDef; 86 87 //////////////////////////////////////////////////////////////////////////////// 88 /// @brief DMA circular normal mode Enumerate definition 89 /// @anchor DMA_circular_normal_mode 90 //////////////////////////////////////////////////////////////////////////////// 91 typedef enum { 92 DMA_Mode_Normal = 0U, 93 DMA_Mode_Circular = DMA_CCR_CIRC // 0x00000020U 94 } DMA_circular_normal_mode_TypeDef; 95 96 //////////////////////////////////////////////////////////////////////////////// 97 /// @brief DMA priority level Enumerate definition 98 /// @anchor DMA_priority_level 99 //////////////////////////////////////////////////////////////////////////////// 100 typedef enum { 101 DMA_Priority_Low = 0U, 102 DMA_Priority_Medium = DMA_CCR_PL_Medium, // 0x00001000U 103 DMA_Priority_High = DMA_CCR_PL_High, // 0x00002000U 104 DMA_Priority_VeryHigh = DMA_CCR_PL_VeryHigh // 0x00003000U 105 } DMA_priority_level_TypeDef; 106 107 //////////////////////////////////////////////////////////////////////////////// 108 /// @brief DMA memory to memory Enumerate definition 109 /// @anchor DMA_memory_to_memory 110 //////////////////////////////////////////////////////////////////////////////// 111 typedef enum { 112 DMA_M2M_Disable = 0U, 113 DMA_M2M_Enable = DMA_CCR_M2M // 0x00004000U 114 } DMA_memory_to_memory_TypeDef; 115 116 //////////////////////////////////////////////////////////////////////////////// 117 /// @brief DMA auto reload Enumerate definition 118 /// @anchor DMA_auto_reload 119 //////////////////////////////////////////////////////////////////////////////// 120 typedef enum { 121 DMA_Auto_Reload_Disable = 0U, // 122 DMA_Auto_Reload_Enable = DMA_CCR_ARE 123 } DMA_auto_reload_TypeDef; 124 /// @brief DMA Interrupt Setting Enumerate definition 125 /// @anchor DMA_auto_reload 126 //////////////////////////////////////////////////////////////////////////////// 127 typedef enum { 128 DMA_IT_TC = DMA_CCR_TCIE, //(0x00000002UL), 129 DMA_IT_HT = DMA_CCR_HTIE, //(0x00000004UL), 130 DMA_IT_TE = DMA_CCR_TEIE, //(0x00000008UL), 131 } DMA_Interrupt_EN_TypeDef; 132 133 134 //////////////////////////////////////////////////////////////////////////////// 135 /// @brief DMA interrupts Enumerate definition 136 /// @anchor DMA_Flags 137 //////////////////////////////////////////////////////////////////////////////// 138 typedef enum { 139 DMAx_IT_GLy = (0x00000001UL), 140 DMAx_IT_TCy = (0x00000002UL), 141 DMAx_IT_HTy = (0x00000004UL), 142 DMAx_IT_TEy = (0x00000008UL), 143 DMA1_IT_GL1 = (0x00000001UL), 144 DMA1_IT_TC1 = (0x00000002UL), 145 DMA1_IT_HT1 = (0x00000004UL), 146 DMA1_IT_TE1 = (0x00000008UL), 147 DMA1_IT_GL2 = (0x00000010UL), 148 DMA1_IT_TC2 = (0x00000020UL), 149 DMA1_IT_HT2 = (0x00000040UL), 150 DMA1_IT_TE2 = (0x00000080UL), 151 DMA1_IT_GL3 = (0x00000100UL), 152 DMA1_IT_TC3 = (0x00000200UL), 153 DMA1_IT_HT3 = (0x00000400UL), 154 DMA1_IT_TE3 = (0x00000800UL), 155 DMA1_IT_GL4 = (0x00001000UL), 156 DMA1_IT_TC4 = (0x00002000UL), 157 DMA1_IT_HT4 = (0x00004000UL), 158 DMA1_IT_TE4 = (0x00008000UL), 159 DMA1_IT_GL5 = (0x00010000UL), 160 DMA1_IT_TC5 = (0x00020000UL), 161 DMA1_IT_HT5 = (0x00040000UL), 162 DMA1_IT_TE5 = (0x00080000UL), 163 DMA1_IT_GL6 = (0x00100000UL), 164 DMA1_IT_TC6 = (0x00200000UL), 165 DMA1_IT_HT6 = (0x00400000UL), 166 DMA1_IT_TE6 = (0x00800000UL), 167 DMA1_IT_GL7 = (0x01000000UL), 168 DMA1_IT_TC7 = (0x02000000UL), 169 DMA1_IT_HT7 = (0x04000000UL), 170 DMA1_IT_TE7 = (0x08000000UL), 171 DMA2_IT_GL1 = (0x10000001UL), 172 DMA2_IT_TC1 = (0x10000002UL), 173 DMA2_IT_HT1 = (0x10000004UL), 174 DMA2_IT_TE1 = (0x10000008UL), 175 DMA2_IT_GL2 = (0x10000010UL), 176 DMA2_IT_TC2 = (0x10000020UL), 177 DMA2_IT_HT2 = (0x10000040UL), 178 DMA2_IT_TE2 = (0x10000080UL), 179 DMA2_IT_GL3 = (0x10000100UL), 180 DMA2_IT_TC3 = (0x10000200UL), 181 DMA2_IT_HT3 = (0x10000400UL), 182 DMA2_IT_TE3 = (0x10000800UL), 183 DMA2_IT_GL4 = (0x10001000UL), 184 DMA2_IT_TC4 = (0x10002000UL), 185 DMA2_IT_HT4 = (0x10004000UL), 186 DMA2_IT_TE4 = (0x10008000UL), 187 DMA2_IT_GL5 = (0x10010000UL), 188 DMA2_IT_TC5 = (0x10020000UL), 189 DMA2_IT_HT5 = (0x10040000UL), 190 DMA2_IT_TE5 = (0x10080000UL), 191 } DMA_Interrupts_TypeDef; 192 typedef enum { 193 DMAx_FLAG_GLy = (0x00000001UL), 194 DMAx_FLAG_TCy = (0x00000002UL), 195 DMAx_FLAG_HTy = (0x00000004UL), 196 DMAx_FLAG_TEy = (0x00000008UL), 197 DMA1_FLAG_GL1 = (0x00000001UL), 198 DMA1_FLAG_TC1 = (0x00000002UL), 199 DMA1_FLAG_HT1 = (0x00000004UL), 200 DMA1_FLAG_TE1 = (0x00000008UL), 201 DMA1_FLAG_GL2 = (0x00000010UL), 202 DMA1_FLAG_TC2 = (0x00000020UL), 203 DMA1_FLAG_HT2 = (0x00000040UL), 204 DMA1_FLAG_TE2 = (0x00000080UL), 205 DMA1_FLAG_GL3 = (0x00000100UL), 206 DMA1_FLAG_TC3 = (0x00000200UL), 207 DMA1_FLAG_HT3 = (0x00000400UL), 208 DMA1_FLAG_TE3 = (0x00000800UL), 209 DMA1_FLAG_GL4 = (0x00001000UL), 210 DMA1_FLAG_TC4 = (0x00002000UL), 211 DMA1_FLAG_HT4 = (0x00004000UL), 212 DMA1_FLAG_TE4 = (0x00008000UL), 213 DMA1_FLAG_GL5 = (0x00010000UL), 214 DMA1_FLAG_TC5 = (0x00020000UL), 215 DMA1_FLAG_HT5 = (0x00040000UL), 216 DMA1_FLAG_TE5 = (0x00080000UL), 217 DMA1_FLAG_GL6 = (0x00100000UL), 218 DMA1_FLAG_TC6 = (0x00200000UL), 219 DMA1_FLAG_HT6 = (0x00400000UL), 220 DMA1_FLAG_TE6 = (0x00800000UL), 221 DMA1_FLAG_GL7 = (0x01000000UL), 222 DMA1_FLAG_TC7 = (0x02000000UL), 223 DMA1_FLAG_HT7 = (0x04000000UL), 224 DMA1_FLAG_TE7 = (0x08000000UL), 225 DMA2_FLAG_GL1 = (0x10000001UL), 226 DMA2_FLAG_TC1 = (0x10000002UL), 227 DMA2_FLAG_HT1 = (0x10000004UL), 228 DMA2_FLAG_TE1 = (0x10000008UL), 229 DMA2_FLAG_GL2 = (0x10000010UL), 230 DMA2_FLAG_TC2 = (0x10000020UL), 231 DMA2_FLAG_HT2 = (0x10000040UL), 232 DMA2_FLAG_TE2 = (0x10000080UL), 233 DMA2_FLAG_GL3 = (0x10000100UL), 234 DMA2_FLAG_TC3 = (0x10000200UL), 235 DMA2_FLAG_HT3 = (0x10000400UL), 236 DMA2_FLAG_TE3 = (0x10000800UL), 237 DMA2_FLAG_GL4 = (0x10001000UL), 238 DMA2_FLAG_TC4 = (0x10002000UL), 239 DMA2_FLAG_HT4 = (0x10004000UL), 240 DMA2_FLAG_TE4 = (0x10008000UL), 241 DMA2_FLAG_GL5 = (0x10010000UL), 242 DMA2_FLAG_TC5 = (0x10020000UL), 243 DMA2_FLAG_HT5 = (0x10040000UL), 244 DMA2_FLAG_TE5 = (0x10080000UL), 245 } DMA_Flags_TypeDef; 246 //////////////////////////////////////////////////////////////////////////////// 247 /// @brief DMA Init structure definition 248 //////////////////////////////////////////////////////////////////////////////// 249 typedef struct { 250 u32 DMA_PeripheralBaseAddr; ///< the peripheral base address for DMA Channeln. 251 u32 DMA_MemoryBaseAddr; ///< the memory base address for DMA Channeln. 252 DMA_data_transfer_direction_TypeDef DMA_DIR; ///< the peripheral is the source or destination. 253 u32 DMA_BufferSize; ///< Specifies the buffer size, in data unit, of the Buffer size 254 DMA_peripheral_incremented_mode_TypeDef DMA_PeripheralInc; ///< Specifies whether the Peripheral address increment or not 255 DMA_memory_incremented_mode_TypeDef DMA_MemoryInc; ///< Specifies whether the memory address register is increment or not 256 DMA_peripheral_data_size_TypeDef DMA_PeripheralDataSize; ///< Specifies the Peripheral data width. 257 DMA_memory_data_size_TypeDef DMA_MemoryDataSize; ///< Specifies the Memory data width. 258 DMA_circular_normal_mode_TypeDef DMA_Mode; ///< Specifies the operation mode of the DMA Channeln circular or normal mode. 259 DMA_priority_level_TypeDef DMA_Priority; ///< Specifies the software priority for the DMA priority level 260 DMA_memory_to_memory_TypeDef DMA_M2M; ///< Specifies if the DMA Channeln will be used in memory-to-memory transfer. 261 DMA_auto_reload_TypeDef DMA_Auto_reload; ///< Specifies if the DMA Channeln will auto reload the CNDTR register 262 } DMA_InitTypeDef; 263 264 /// @} 265 266 //////////////////////////////////////////////////////////////////////////////// 267 /// @defgroup DMA_Exported_Variables 268 /// @{ 269 #ifdef _HAL_DMA_C_ 270 271 #define GLOBAL 272 #else 273 #define GLOBAL extern 274 #endif 275 276 #undef GLOBAL 277 /// @} 278 279 //////////////////////////////////////////////////////////////////////////////// 280 /// @defgroup DMA_Exported_Functions 281 /// @{ 282 283 void DMA_DeInit(DMA_Channel_TypeDef* channel); 284 void DMA_Init(DMA_Channel_TypeDef* channel, DMA_InitTypeDef* init_struct); 285 void DMA_StructInit(DMA_InitTypeDef* init_struct); 286 void DMA_Cmd(DMA_Channel_TypeDef* channel, FunctionalState state); 287 void DMA_ITConfig(DMA_Channel_TypeDef* channel, DMA_Interrupt_EN_TypeDef it, FunctionalState state); 288 void DMA_ClearFlag(DMA_Flags_TypeDef flag); 289 void DMA_ClearITPendingBit(DMA_Interrupts_TypeDef it); 290 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* channel, u16 length); 291 u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* channel); 292 FlagStatus DMA_GetFlagStatus(DMA_Flags_TypeDef flag); 293 ITStatus DMA_GetITStatus(DMA_Interrupts_TypeDef it); 294 295 void exDMA_SetPeripheralAddress(DMA_Channel_TypeDef* channel, u32 addr); 296 void exDMA_SetTransmitLen(DMA_Channel_TypeDef* channel, u16 len); 297 void exDMA_SetMemoryAddress(DMA_Channel_TypeDef* channel, u32 addr); 298 299 /// @} 300 301 /// @} 302 303 /// @} 304 //////////////////////////////////////////////////////////////////////////////// 305 #endif //__HAL_DMA_H 306 //////////////////////////////////////////////////////////////////////////////// 307