1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file hal_fsmc.c 3 /// @author AE TEAM 4 /// @brief THIS FILE PROVIDES ALL THE FSMC FIRMWARE FUNCTIONS. 5 /// Interface with SRAM, PSRAM, NOR memories 6 /// Interrupts and flags management 7 //////////////////////////////////////////////////////////////////////////////// 8 /// @attention 9 /// 10 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 11 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 12 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 13 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 14 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 15 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 16 /// 17 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 18 //////////////////////////////////////////////////////////////////////////////// 19 20 // Define to prevent recursive inclusion 21 #define _HAL_FSMC_C_ 22 23 // Files includes 24 #include "reg_rcc.h" 25 #include "reg_syscfg.h" 26 #include "hal_fsmc.h" 27 28 29 //////////////////////////////////////////////////////////////////////////////// 30 /// @addtogroup MM32_Hardware_Abstract_Layer 31 /// @{ 32 33 //////////////////////////////////////////////////////////////////////////////// 34 /// @addtogroup FSMC_HAL 35 /// @{ 36 37 //////////////////////////////////////////////////////////////////////////////// 38 /// @addtogroup FSMC_Exported_Functions 39 /// @{ 40 41 FSMC_NORSRAMStructInit(FSMC_InitTypeDef * init_struct)42void FSMC_NORSRAMStructInit(FSMC_InitTypeDef* init_struct) 43 { 44 init_struct->FSMC_Mode = FSMC_Mode_NorFlash; 45 init_struct->FSMC_AddrDataMode = FSMC_AddrDataDeMUX; 46 47 init_struct->FSMC_TimingRegSelect = FSMC_TimingRegSelect_0; 48 init_struct->FSMC_MemSize = FSMC_MemSize_64MB; 49 init_struct->FSMC_MemType = FSMC_MemType_NorSRAM; 50 } FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef * init_struct)51void FSMC_NORSRAM_BankStructInit(FSMC_NORSRAM_Bank_InitTypeDef* init_struct) 52 { 53 54 init_struct->FSMC_SMReadPipe = 0; 55 init_struct->FSMC_ReadyMode = 0; 56 init_struct->FSMC_WritePeriod = 0x2; 57 init_struct->FSMC_WriteHoldTime = 1; 58 init_struct->FSMC_AddrSetTime = 3; 59 init_struct->FSMC_ReadPeriod = 0x1; 60 init_struct->FSMC_DataWidth = FSMC_DataWidth_16bits; 61 } FSMC_NORSRAMInit(FSMC_InitTypeDef * init_struct)62void FSMC_NORSRAMInit(FSMC_InitTypeDef* init_struct) 63 { 64 SYSCFG->CFGR &= ~(SYSCFG_CFGR_FSMC_MODE | SYSCFG_CFGR_FSMC_AF_ADDR | SYSCFG_CFGR_FSMC_SYNC_EN); 65 SYSCFG->CFGR |= (u32)init_struct->FSMC_Mode | \ 66 (u32)init_struct->FSMC_AddrDataMode; 67 68 FSMC->SMSKR = (u32)init_struct->FSMC_TimingRegSelect | \ 69 (u32)init_struct->FSMC_MemSize | \ 70 (u32)init_struct->FSMC_MemType; 71 } 72 //////////////////////////////////////////////////////////////////////////////// 73 /// @brief Initialize the FSMC_NORSRAM Timing according to the specified 74 /// parameters in the FSMC_NORSRAM_TimingTypeDef 75 /// @param FSMC_Bank_InitStruct: Timing Pointer to NORSRAM Timing structure 76 /// @param Bank: NORSRAM bank number 77 /// @retval None. 78 //////////////////////////////////////////////////////////////////////////////// FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef * FSMC_Bank_InitStruct,FSMC_NORSRAM_BANK_TypeDef bank)79void FSMC_NORSRAM_Bank_Init(FSMC_NORSRAM_Bank_InitTypeDef* FSMC_Bank_InitStruct, FSMC_NORSRAM_BANK_TypeDef bank) 80 { 81 // Set FSMC_NORSRAM device timing parameters 82 if(bank == FSMC_NORSRAM_BANK0) { 83 FSMC->SMTMGR_SET0 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ 84 (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ 85 (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ 86 (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ 87 (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ 88 (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; 89 FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET0; 90 FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET0_Pos; 91 } 92 else if(bank == FSMC_NORSRAM_BANK1) { 93 FSMC->SMTMGR_SET1 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ 94 (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ 95 (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ 96 (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ 97 (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ 98 (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; 99 FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET1; 100 FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET1_Pos; 101 } 102 else if(bank == FSMC_NORSRAM_BANK2) { 103 FSMC->SMTMGR_SET2 = (u32)(FSMC_Bank_InitStruct->FSMC_SMReadPipe << FSMC_SMTMGR_SET_SM_READ_PIPE_Pos) | \ 104 (u32)(FSMC_Bank_InitStruct->FSMC_ReadyMode << FSMC_SMTMGR_SET_READ_MODE_Pos) | \ 105 (u32)(FSMC_Bank_InitStruct->FSMC_WritePeriod << FSMC_SMTMGR_SET_T_WP_Pos) | \ 106 (u32)(FSMC_Bank_InitStruct->FSMC_WriteHoldTime << FSMC_SMTMGR_SET_T_WR_Pos) | \ 107 (u32)(FSMC_Bank_InitStruct->FSMC_AddrSetTime << FSMC_SMTMGR_SET_T_AS_Pos) | \ 108 (u32)(FSMC_Bank_InitStruct->FSMC_ReadPeriod << FSMC_SMTMGR_SET_T_RC_Pos ) ; 109 FSMC->SMCTLR &= ~FSMC_SMCTLR_SM_DATA_WIDTH_SET2; 110 FSMC->SMCTLR |= (FSMC_Bank_InitStruct->FSMC_DataWidth) << FSMC_SMCTLR_SM_DATA_WIDTH_SET2_Pos; 111 } 112 } 113 114 115 116 117 /// @} 118 119 /// @} 120 121 /// @} 122 123 //////////////////////////////////////////////////////////////////////////////// 124 //////////////////////////////////////////////////////////////////////////////// 125