1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_can.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_CAN_H 22 #define __REG_CAN_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 //////////////////////////////////////////////////////////////////////////////// 44 /// @brief CAN Base Address Definition 45 //////////////////////////////////////////////////////////////////////////////// 46 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) ///< Base Address: 0x40006400 47 48 49 50 51 //////////////////////////////////////////////////////////////////////////////// 52 /// @brief CAN Register Structure Definition 53 //////////////////////////////////////////////////////////////////////////////// 54 55 //////////////////////////////////////////////////////////////////////////////// 56 /// @brief CAN basic 57 //////////////////////////////////////////////////////////////////////////////// 58 typedef struct { 59 __IO u32 CR; ///< Control register, offset: 0x00 60 __IO u32 CMR; ///< Command register, offset: 0x04 61 __IO u32 SR; ///< <Status register, offset: 0x08 62 __IO u32 IR; ///< Interrupt register, offset: 0x0c 63 __IO u32 ACR; ///< Acceptance Code register, offset: 0x10 64 __IO u32 AMR; ///< Acceptance Mask register, offset: 0x14 65 __IO u32 BTR0; ///< Bus Timing register 0, offset: 0x18 66 __IO u32 BTR1; ///< Bus Timing register 1, offset: 0x1C 67 __IO u32 RESERVED0; 68 __IO u32 RESERVED1; 69 __IO u32 TXID0; ///< Send ID register 0, offset: 0x28 70 __IO u32 TXID1; ///< Send ID register 1, offset: 0x2c 71 __IO u32 TXDR0; ///< Send Data register 0, offset: 0x30 72 __IO u32 TXDR1; ///< Send Data register 1, offset: 0x34 73 __IO u32 TXDR2; ///< Send Data register 2, offset: 0x38 74 __IO u32 TXDR3; ///< Send Data register 3, offset: 0x3c 75 __IO u32 TXDR4; ///< Send Data register 4, offset: 0x40 76 __IO u32 TXDR5; ///< Send Data register 5, offset: 0x44 77 __IO u32 TXDR6; ///< Send Data register 6, offset: 0x48 78 __IO u32 TXDR7; ///< Send Data register 7, offset: 0x4c 79 __IO u32 RXID0; ///< Mode register, offset: 0x50 80 __IO u32 RXID1; ///< Mode register, offset: 0x54 81 __IO u32 RXDR0; ///< Mode register, offset: 0x58 82 __IO u32 RXDR1; ///< Mode register, offset: 0x5C 83 __IO u32 RXDR2; ///< Mode register, offset: 0x60 84 __IO u32 RXDR3; ///< Mode register, offset: 0x64 85 __IO u32 RXDR4; ///< Mode register, offset: 0x68 86 __IO u32 RXDR5; ///< Mode register, offset: 0x6c 87 __IO u32 RXDR6; ///< Mode register, offset: 0x70 88 __IO u32 RXDR7; ///< Mode register, offset: 0x74 89 __IO u32 RESERVED2; 90 __IO u32 CDR; ///< Clock Divider register, offset: 0x7c 91 } CAN_TypeDef; 92 93 //////////////////////////////////////////////////////////////////////////////// 94 /// @brief CAN Peli 95 //////////////////////////////////////////////////////////////////////////////// 96 typedef struct { 97 __IO u32 MOD; ///< Mode register, offset: 0x00 98 __IO u32 CMR; ///< Command register, offset: 0x04 99 __IO u32 SR; ///< Status register, offset: 0x08 100 __IO u32 IR; ///< Interrupt Enable register, offset: 0x0c 101 __IO u32 IER; ///< Mode register, offset: 0x10 102 __IO u32 RESERVED0; 103 __IO u32 BTR0; ///< Bus Timing register 0, offset: 0x18 104 __IO u32 BTR1; ///< Bus Timing register 1, offset: 0x1C 105 __IO u32 RESERVED1; 106 __IO u32 RESERVED2; 107 __IO u32 RESERVED3; 108 __IO u32 ALC; ///< Arbitration Lost Capture register, offset: 0x2c 109 __IO u32 ECC; ///< Error Code Capture register, offset: 0x30 110 __IO u32 EWLR; ///< Error Warning Limit register, offset: 0x34 111 __IO u32 RXERR; ///< RX Error Counter register, offset: 0x38 112 __IO u32 TXERR; ///< TX Error Counter register, offset: 0x3c 113 __IO u32 FF; ///< Frame Format register, offset: 0x40 114 __IO u32 ID0; ///< ID register 0, offset: 0x44 115 __IO u32 ID1; ///< ID register 1, offset: 0x48 116 __IO u32 DATA0; ///< Data register 0, offset: 0x4c 117 __IO u32 DATA1; ///< Data register 1, offset: 0x50 118 __IO u32 DATA2; ///< Data register 2, offset: 0x54 119 __IO u32 DATA3; ///< Data register 3, offset: 0x58 120 __IO u32 DATA4; ///< Data register 4, offset: 0x5c 121 __IO u32 DATA5; ///< Data register 5, offset: 0x60 122 __IO u32 DATA6; ///< Data register 6, offset: 0x64 123 __IO u32 DATA7; ///< Data register 7, offset: 0x68 124 __IO u32 DATA8; ///< Data register 8, offset: 0x6c 125 __IO u32 DATA9; ///< Data register 9, offset: 0x70 126 __IO u32 RMC; ///< RMC register, offset: 0x74 127 __IO u32 RBSA; ///< RBSA register, offset: 0x78 128 __IO u32 CDR; ///< Clock Divider register offset: 0x7c 129 } CAN_Peli_TypeDef; 130 //////////////////////////////////////////////////////////////////////////////// 131 /// @brief CAN type pointer Definition 132 //////////////////////////////////////////////////////////////////////////////// 133 typedef struct { 134 __IO u32 ACR0; 135 __IO u32 ACR1; 136 __IO u32 ACR2; 137 __IO u32 ACR3; 138 __IO u32 AMR0; 139 __IO u32 AMR1; 140 __IO u32 AMR2; 141 __IO u32 AMR3; 142 } CAN_FLT_GROUP; 143 144 typedef struct { 145 CAN_FLT_GROUP GROUP0; //Address offset: 0x40 146 u32 RESERVED[8]; //Address offset: 0x60 147 __IO u32 AFM0; //Address offset: 0x80 148 __IO u32 AFM1; //Address offset: 0x84 149 __IO u32 AFM2; //Address offset: 0x88 150 __IO u32 FGA0; //Address offset: 0x8C 151 __IO u32 FGA1; //Address offset: 0x90 152 __IO u32 FGA2; //Address offset: 0x94 153 CAN_FLT_GROUP GROUP1; //Address offset: 0x98 154 CAN_FLT_GROUP GROUP2; //Address offset: 0xB8 155 CAN_FLT_GROUP GROUP3; //Address offset: 0xD8 156 CAN_FLT_GROUP GROUP4; //Address offset: 0xF8 157 CAN_FLT_GROUP GROUP5; //Address offset: 0x118 158 CAN_FLT_GROUP GROUP6; //Address offset: 0x138 159 CAN_FLT_GROUP GROUP7; //Address offset: 0x158 160 CAN_FLT_GROUP GROUP8; //Address offset: 0x178 161 CAN_FLT_GROUP GROUP9; //Address offset: 0x198 162 CAN_FLT_GROUP GROUP10; //Address offset: 0x1B8 163 CAN_FLT_GROUP GROUP11; //Address offset: 0x1D8 164 CAN_FLT_GROUP GROUP12; //Address offset: 0x1F8 165 CAN_FLT_GROUP GROUP13; //Address offset: 0x218 166 CAN_FLT_GROUP GROUP14; //Address offset: 0x238 167 CAN_FLT_GROUP GROUP15; //Address offset: 0x258 168 CAN_FLT_GROUP GROUP16; //Address offset: 0x278 169 CAN_FLT_GROUP GROUP17; //Address offset: 0x298 170 CAN_FLT_GROUP GROUP18; //Address offset: 0x2B8 171 CAN_FLT_GROUP GROUP19; //Address offset: 0x2D8 172 } CAN_Peli_FLT_TypeDef; 173 174 175 176 //////////////////////////////////////////////////////////////////////////////// 177 /// @brief CAN type pointer Definition 178 //////////////////////////////////////////////////////////////////////////////// 179 #define CAN1 ((CAN_TypeDef*) CAN1_BASE) 180 #define CAN1_PELI ((CAN_Peli_TypeDef*) CAN1_BASE) 181 #define CAN_Peli_FLT ((CAN_Peli_FLT_TypeDef*)(CAN1_BASE + 0x40)) 182 183 184 185 //////////////////////////////////////////////////////////////////////////////// 186 /// @brief CAN basic 187 //////////////////////////////////////////////////////////////////////////////// 188 //////////////////////////////////////////////////////////////////////////////// 189 /// @brief CAN_CR register Bit definition 190 //////////////////////////////////////////////////////////////////////////////// 191 #define CAN_CR_RR_Pos (0) 192 #define CAN_CR_RR (0x01U << CAN_CR_RR_Pos) ///< CAN reset request 193 #define CAN_CR_RIE_Pos (1) 194 #define CAN_CR_RIE (0x01U << CAN_CR_RIE_Pos) ///< CAN receive interrupt enable 195 #define CAN_CR_TIE_Pos (2) 196 #define CAN_CR_TIE (0x01U << CAN_CR_TIE_Pos) ///< CAN transmit interrupt enable 197 #define CAN_CR_EIE_Pos (3) 198 #define CAN_CR_EIE (0x01U << CAN_CR_EIE_Pos) ///< CAN error interrupt enable 199 #define CAN_CR_OIE_Pos (4) 200 #define CAN_CR_OIE (0x01U << CAN_CR_OIE_Pos) ///< CAN overflow interrupt enable 201 202 //////////////////////////////////////////////////////////////////////////////// 203 /// @brief CAN_CMR register Bit definition 204 //////////////////////////////////////////////////////////////////////////////// 205 #define CAN_CMR_TR_Pos (0) 206 #define CAN_CMR_TR (0x01U << CAN_CMR_TR_Pos ) ///< CAN transmission request 207 #define CAN_CMR_AT_Pos (1) 208 #define CAN_CMR_AT (0x01U << CAN_CMR_AT_Pos ) ///< CAN abort transmission 209 #define CAN_CMR_RRB_Pos (2) 210 #define CAN_CMR_RRB (0x01U << CAN_CMR_RRB_Pos) ///< CAN release receive buffer 211 #define CAN_CMR_CDO_Pos (3) 212 #define CAN_CMR_CDO (0x01U << CAN_CMR_CDO_Pos) ///< CAN clear data overrun 213 #define CAN_CMR_GTS_Pos (4) 214 #define CAN_CMR_GTS (0x01U << CAN_CMR_GTS_Pos) ///< CAN go to sleep 215 216 //////////////////////////////////////////////////////////////////////////////// 217 /// @brief CAN_SR register Bit definition 218 //////////////////////////////////////////////////////////////////////////////// 219 #define CAN_SR_RBS_Pos (0) 220 #define CAN_SR_RBS (0x01U << CAN_SR_RBS_Pos) ///< CAN receive buffer status 221 #define CAN_SR_DOS_Pos (1) 222 #define CAN_SR_DOS (0x01U << CAN_SR_DOS_Pos) ///< CAN data overrun status 223 #define CAN_SR_TBS_Pos (2) 224 #define CAN_SR_TBS (0x01U << CAN_SR_TBS_Pos) ///< CAN transmit buffer status 225 #define CAN_SR_TCS_Pos (3) 226 #define CAN_SR_TCS (0x01U << CAN_SR_TCS_Pos) ///< CAN transmission complete status 227 #define CAN_SR_RS_Pos (4) 228 #define CAN_SR_RS (0x01U << CAN_SR_RS_Pos) ///< CAN receive status 229 #define CAN_SR_TS_Pos (5) 230 #define CAN_SR_TS (0x01U << CAN_SR_TS_Pos) ///< CAN transmit status 231 #define CAN_SR_ES_Pos (6) 232 #define CAN_SR_ES (0x01U << CAN_SR_ES_Pos) ///< CAN error status 233 #define CAN_SR_BS_Pos (7) 234 #define CAN_SR_BS (0x01U << CAN_SR_BS_Pos) ///< CAN bus status 235 236 //////////////////////////////////////////////////////////////////////////////// 237 /// @brief CAN_ACR register Bit definition 238 //////////////////////////////////////////////////////////////////////////////// 239 #define CAN_ACR_AC (0xFFU << 0) ///< CAN acceptance code 240 241 //////////////////////////////////////////////////////////////////////////////// 242 /// @brief CAN_AMR register Bit definition 243 //////////////////////////////////////////////////////////////////////////////// 244 #define CAN_AMR_AM_Pos (0) 245 #define CAN_AMR_AM (0xFFU << CAN_AMR_AM_Pos) ///< CAN acceptance mask 246 247 //////////////////////////////////////////////////////////////////////////////// 248 /// @brief CAN_BTR0 register Bit definition 249 //////////////////////////////////////////////////////////////////////////////// 250 #define CAN_BTR0_BRP_Pos (0) 251 #define CAN_BTR0_BRP (0x003FU << CAN_BTR0_BRP_Pos) ///< CAN baud rate prescaler 252 #define CAN_BTR0_SJW_Pos (6) 253 #define CAN_BTR0_SJW (0x03U << CAN_BTR0_SJW_Pos) ///< CAN synchronization jump width 254 255 //////////////////////////////////////////////////////////////////////////////// 256 /// @brief CAN_BTR1 register Bit definition 257 //////////////////////////////////////////////////////////////////////////////// 258 #define CAN_BTR1_TESG1_Pos (0) 259 #define CAN_BTR1_TESG1 (0x000FU << CAN_BTR1_TESG1_Pos) ///< CAN Time segment 1 260 #define CAN_BTR1_TESG2_Pos (4) 261 #define CAN_BTR1_TESG2 (0x07U << CAN_BTR1_TESG2_Pos) ///< CAN Time segment 2 262 #define CAN_BTR1_SAM_Pos (7) 263 #define CAN_BTR1_SAM (0x01U << CAN_BTR1_SAM_Pos) ///< CAN sampling 264 265 //////////////////////////////////////////////////////////////////////////////// 266 /// @brief CAN_TXID0 register Bit definition 267 //////////////////////////////////////////////////////////////////////////////// 268 #define CAN_TXID0_ID_3_Pos (0) 269 #define CAN_TXID0_ID_3 (0x01U << CAN_TXID0_ID_3_Pos) ///< CAN identifier byte 3 270 #define CAN_TXID0_ID_4_Pos (1) 271 #define CAN_TXID0_ID_4 (0x01U << CAN_TXID0_ID_4_Pos) ///< CAN identifier byte 4 272 #define CAN_TXID0_ID_5_Pos (2) 273 #define CAN_TXID0_ID_5 (0x01U << CAN_TXID0_ID_5_Pos) ///< CAN identifier byte 5 274 #define CAN_TXID0_ID_6_Pos (3) 275 #define CAN_TXID0_ID_6 (0x01U << CAN_TXID0_ID_6_Pos) ///< CAN identifier byte 6 276 #define CAN_TXID0_ID_7_Pos (4) 277 #define CAN_TXID0_ID_7 (0x01U << CAN_TXID0_ID_7_Pos) ///< CAN identifier byte 7 278 #define CAN_TXID0_ID_8_Pos (5) 279 #define CAN_TXID0_ID_8 (0x01U << CAN_TXID0_ID_8_Pos) ///< CAN identifier byte 8 280 #define CAN_TXID0_ID_9_Pos (6) 281 #define CAN_TXID0_ID_9 (0x01U << CAN_TXID0_ID_9_Pos) ///< CAN identifier byte 9 282 #define CAN_TXID0_ID_10_Pos (7) 283 #define CAN_TXID0_ID_10 (0x01U << CAN_TXID0_ID_10_Pos) ///< CAN identifier byte 10 284 285 //////////////////////////////////////////////////////////////////////////////// 286 /// @brief CAN_TXID1 register Bit definition 287 //////////////////////////////////////////////////////////////////////////////// 288 #define CAN_TXID1_DLC0_Pos (0) 289 #define CAN_TXID1_DLC0 (0x01U << CAN_TXID1_DLC0_Pos) ///< CAN data length code 0 ~ 8 290 #define CAN_TXID1_DLC1_Pos (1) 291 #define CAN_TXID1_DLC1 (0x01U << CAN_TXID1_DLC1_Pos) ///< CAN data length code 0 ~ 8 292 #define CAN_TXID1_DLC2_Pos (2) 293 #define CAN_TXID1_DLC2 (0x01U << CAN_TXID1_DLC2_Pos) ///< CAN data length code 0 ~ 8 294 #define CAN_TXID1_DLC3_Pos (3) 295 #define CAN_TXID1_DLC3 (0x01U << CAN_TXID1_DLC3_Pos) ///< CAN data length code 0 ~ 8 296 #define CAN_TXID1_RTR_Pos (4) 297 #define CAN_TXID1_RTR (0x01U << CAN_TXID1_RTR_Pos ) ///< CAN remote transmission request 298 #define CAN_TXID1_ID_0_Pos (5) 299 #define CAN_TXID1_ID_0 (0x01U << CAN_TXID1_ID_0_Pos) ///< CAN identifier byte 0 300 #define CAN_TXID1_ID_1_Pos (6) 301 #define CAN_TXID1_ID_1 (0x01U << CAN_TXID1_ID_1_Pos) ///< CAN identifier byte 1 302 #define CAN_TXID1_ID_2_Pos (7) 303 #define CAN_TXID1_ID_2 (0x01U << CAN_TXID1_ID_2_Pos) ///< CAN identifier byte 2 304 305 //////////////////////////////////////////////////////////////////////////////// 306 /// @brief CAN_TXDRn register Bit definition 307 //////////////////////////////////////////////////////////////////////////////// 308 #define CAN_TXDRn (0x00FFU) // (n = 0..7) ///< CAN send data 309 310 //////////////////////////////////////////////////////////////////////////////// 311 /// @brief CAN_CDR register Bit definition 312 //////////////////////////////////////////////////////////////////////////////// 313 #define CAN_CDR_MODE_Pos (7) 314 #define CAN_CDR_MODE (0x01U << CAN_CDR_MODE_Pos) ///< CAN mode 315 316 //////////////////////////////////////////////////////////////////////////////// 317 /// @brief CAN Peli 318 //////////////////////////////////////////////////////////////////////////////// 319 //////////////////////////////////////////////////////////////////////////////// 320 /// @brief CAN_MOD register Bit definition 321 //////////////////////////////////////////////////////////////////////////////// 322 #define CAN_MOD_RM_Pos (0) 323 #define CAN_MOD_RM (0x01U << CAN_MOD_RM_Pos) ///< CAN reset mode 324 #define CAN_MOD_LOM_Pos (1) 325 #define CAN_MOD_LOM (0x01U << CAN_MOD_LOM_Pos) ///< CAN listen only mode 326 #define CAN_MOD_STM_Pos (2) 327 #define CAN_MOD_STM (0x01U << CAN_MOD_STM_Pos) ///< CAN self test mode 328 #define CAN_MOD_AFM_Pos (3) 329 #define CAN_MOD_AFM (0x01U << CAN_MOD_AFM_Pos) ///< CAN acceptance filter mode 330 331 //////////////////////////////////////////////////////////////////////////////// 332 /// @brief CAN_CMR register Bit definition 333 //////////////////////////////////////////////////////////////////////////////// 334 #define CAN_CMR_TR_Pos (0) 335 #define CAN_CMR_TR (0x01U << CAN_CMR_TR_Pos ) ///< CAN transmission request 336 #define CAN_CMR_AT_Pos (1) 337 #define CAN_CMR_AT (0x01U << CAN_CMR_AT_Pos ) ///< CAN abort transmission 338 #define CAN_CMR_RRB_Pos (2) 339 #define CAN_CMR_RRB (0x01U << CAN_CMR_RRB_Pos) ///< CAN release receive buffer 340 #define CAN_CMR_CDO_Pos (3) 341 #define CAN_CMR_CDO (0x01U << CAN_CMR_CDO_Pos) ///< CAN clear data overrun 342 #define CAN_CMR_SRR_Pos (4) 343 #define CAN_CMR_SRR (0x01U << CAN_CMR_SRR_Pos) ///< CAN self reset request 344 345 //////////////////////////////////////////////////////////////////////////////// 346 /// @brief CAN_SR register Bit definition 347 //////////////////////////////////////////////////////////////////////////////// 348 #define CAN_SR_RBS_Pos (0) 349 #define CAN_SR_RBS (0x01U << CAN_SR_RBS_Pos) ///< CAN receive buffer status 350 #define CAN_SR_DOS_Pos (1) 351 #define CAN_SR_DOS (0x01U << CAN_SR_DOS_Pos) ///< CAN data overrun status 352 #define CAN_SR_TBS_Pos (2) 353 #define CAN_SR_TBS (0x01U << CAN_SR_TBS_Pos) ///< CAN transmit buffer status 354 #define CAN_SR_TCS_Pos (3) 355 #define CAN_SR_TCS (0x01U << CAN_SR_TCS_Pos) ///< CAN transmission complete status 356 #define CAN_SR_RS_Pos (4) 357 #define CAN_SR_RS (0x01U << CAN_SR_RS_Pos) ///< CAN receive status 358 #define CAN_SR_TS_Pos (5) 359 #define CAN_SR_TS (0x01U << CAN_SR_TS_Pos) ///< CAN transmit status 360 #define CAN_SR_ES_Pos (6) 361 #define CAN_SR_ES (0x01U << CAN_SR_ES_Pos) ///< CAN error status 362 #define CAN_SR_BS_Pos (7) 363 #define CAN_SR_BS (0x01U << CAN_SR_BS_Pos) ///< CAN bus status 364 365 //////////////////////////////////////////////////////////////////////////////// 366 /// @brief CAN_IR register Bit definition 367 //////////////////////////////////////////////////////////////////////////////// 368 #define CAN_IR_RI_Pos (0) 369 #define CAN_IR_RI (0x01U << CAN_IR_RI_Pos) ///< CAN receive interrupt 370 #define CAN_IR_TI_Pos (1) 371 #define CAN_IR_TI (0x01U << CAN_IR_TI_Pos) ///< CAN transmit interrupt 372 #define CAN_IR_EI_Pos (2) 373 #define CAN_IR_EI (0x01U << CAN_IR_EI_Pos) ///< CAN error interrupt 374 #define CAN_IR_DOI_Pos (3) 375 #define CAN_IR_DOI (0x01U << CAN_IR_DOI_Pos) ///< CAN data overrun interrupt 376 #define CAN_IR_EPI_Pos (5) 377 #define CAN_IR_EPI (0x01U << CAN_IR_EPI_Pos) ///< CAN error passive interrupt 378 #define CAN_IR_ALI_Pos (6) 379 #define CAN_IR_ALI (0x01U << CAN_IR_ALI_Pos) ///< CAN arbitration lost interrupt 380 #define CAN_IR_BEI_Pos (7) 381 #define CAN_IR_BEI (0x01U << CAN_IR_BEI_Pos) ///< CAN bus error interrupt 382 383 //////////////////////////////////////////////////////////////////////////////// 384 /// @brief CAN_IR register Bit definition 385 //////////////////////////////////////////////////////////////////////////////// 386 #define CAN_IER_RIE_Pos (0) 387 #define CAN_IER_RIE (0x01U << CAN_IER_RIE_Pos) ///< CAN receive interrupt enable 388 #define CAN_IER_TIE_Pos (1) 389 #define CAN_IER_TIE (0x01U << CAN_IER_TIE_Pos) ///< CAN transmit interrupt enable 390 #define CAN_IER_EIE_Pos (2) 391 #define CAN_IER_EIE (0x01U << CAN_IER_EIE_Pos) ///< CAN error interrupt enable 392 #define CAN_IER_DOIE_Pos (3) 393 #define CAN_IER_DOIE (0x01U << CAN_IER_DOIE_Pos) ///< CAN data overrun interrupt enable 394 #define CAN_IER_EPIE_Pos (5) 395 #define CAN_IER_EPIE (0x01U << CAN_IER_EPI_Pos) ///< CAN error passive interrupt enable 396 #define CAN_IER_ALIE_Pos (6) 397 #define CAN_IER_ALIE (0x01U << CAN_IER_ALIE_Pos) ///< CAN arbitration lost interrupt enable 398 #define CAN_IER_BEIE_Pos (7) 399 #define CAN_IER_BEIE (0x01U << CAN_IER_BEIE_Pos) ///< CAN bus error interrupt enable 400 401 //////////////////////////////////////////////////////////////////////////////// 402 /// @brief CAN_ACRn register Bit definition 403 //////////////////////////////////////////////////////////////////////////////// 404 #define CAN_ACRn_AC_Pos (0) 405 #define CAN_ACRn_AC (0xFFU << CAN_ACRn_AC_Pos) ///< CAN acceptance code 406 407 //////////////////////////////////////////////////////////////////////////////// 408 /// @brief CAN_AMRn register Bit definition 409 //////////////////////////////////////////////////////////////////////////////// 410 #define CAN_AMRn_AM_Pos (0) 411 #define CAN_AMRn_AM (0xFFU << CAN_AMRn_AM_Pos) ///< CAN acceptance mask 412 413 //////////////////////////////////////////////////////////////////////////////// 414 /// @brief CAN_BTR0 register Bit definition 415 //////////////////////////////////////////////////////////////////////////////// 416 #define CAN_BTR0_BRP_Pos (0) 417 #define CAN_BTR0_BRP (0x003FU << CAN_BTR0_BRP_Pos) ///< CAN baud rate prescaler 418 #define CAN_BTR0_SJW_Pos (6) 419 #define CAN_BTR0_SJW (0x03U << CAN_BTR0_SJW_Pos) ///< CAN synchronization jump width 420 421 //////////////////////////////////////////////////////////////////////////////// 422 /// @brief CAN_ALC register Bit definition 423 //////////////////////////////////////////////////////////////////////////////// 424 #define CAN_ALC_BITNO_Pos (0) 425 #define CAN_ALC_BITNO (0x001FU << CAN_ALC_BITNO_Pos) ///< CAN bit number 426 427 //////////////////////////////////////////////////////////////////////////////// 428 /// @brief CAN_ECC register Bit definition 429 //////////////////////////////////////////////////////////////////////////////// 430 #define CAN_ECC_SEG_Pos (0) 431 #define CAN_ECC_SEG (0x001FU <<CAN_ECC_SEG_Pos) ///< CAN error code capture 432 #define CAN_ECC_DIR_Pos (5) 433 #define CAN_ECC_DIR (0x01U << CAN_ECC_DIR_Pos) ///< CAN direction 434 #define CAN_ECC_ERRC_Pos (6) 435 #define CAN_ECC_ERRC (0x03U << CAN_ECC_ERRC_Pos) ///< CAN error code 436 437 //////////////////////////////////////////////////////////////////////////////// 438 /// @brief CAN_EWLR register Bit definition 439 //////////////////////////////////////////////////////////////////////////////// 440 #define CAN_EWLR_EWL_Pos (0) 441 #define CAN_EWLR_EWL (0x00FFU << CAN_EWLR_EWL_Pos) ///< CAN programmable error warning limit 442 443 //////////////////////////////////////////////////////////////////////////////// 444 /// @brief CAN_RXERR register Bit definition 445 //////////////////////////////////////////////////////////////////////////////// 446 #define CAN_RXERR_RXERR_Pos (0) 447 #define CAN_RXERR_RXERR (0x00FFU << CAN_RXERR_RXERR_Pos) ///< CAN RX error counter register 448 449 //////////////////////////////////////////////////////////////////////////////// 450 /// @brief CAN_TXERR register Bit definition 451 //////////////////////////////////////////////////////////////////////////////// 452 #define CAN_TXERR_TXERR_Pos (0) 453 #define CAN_TXERR_TXERR (0x00FFU << CAN_TXERR_TXERR_Pos) ///< CAN TX error counter register 454 455 //////////////////////////////////////////////////////////////////////////////// 456 /// @brief CAN_FF register Bit definition 457 //////////////////////////////////////////////////////////////////////////////// 458 #define CAN_FF_DLC_0_Pos (0) 459 #define CAN_FF_DLC_0 (0x01U << CAN_FF_DLC_0_Pos) ///< CAN data length code bit 460 #define CAN_FF_DLC_1_Pos (1) 461 #define CAN_FF_DLC_1 (0x01U << CAN_FF_DLC_1_Pos) ///< CAN data length code bit 462 #define CAN_FF_DLC_2_Pos (2) 463 #define CAN_FF_DLC_2 (0x01U << CAN_FF_DLC_2_Pos) ///< CAN data length code bit 464 #define CAN_FF_DLC_3_Pos (3) 465 #define CAN_FF_DLC_3 (0x01U << CAN_FF_DLC_3_Pos) ///< CAN data length code bit 466 #define CAN_FF_RTR_Pos (6) 467 #define CAN_FF_RTR (0x01U << CAN_FF_RTR_Pos) ///< CAN remote transmission request 468 #define CAN_FF_FF_Pos (7) 469 #define CAN_FF_FF (0x01U << CAN_FF_FF_Pos) ///< CAN frame format 470 //////////////////////////////////////////////////////////////////////////////// 471 /// @brief CAN_TXID0 register Bit definition 472 //////////////////////////////////////////////////////////////////////////////// 473 #define CAN_TXID0_ID_21_Pos (0) 474 #define CAN_TXID0_ID_21 (0x01U << CAN_TXID0_ID_21_Pos) ///< CAN identifier bit 21 475 #define CAN_TXID0_ID_22_Pos (1) 476 #define CAN_TXID0_ID_22 (0x01U << CAN_TXID0_ID_22_Pos) ///< CAN identifier bit 22 477 #define CAN_TXID0_ID_23_Pos (2) 478 #define CAN_TXID0_ID_23 (0x01U << CAN_TXID0_ID_23_Pos) ///< CAN identifier bit 23 479 #define CAN_TXID0_ID_24_Pos (3) 480 #define CAN_TXID0_ID_24 (0x01U << CAN_TXID0_ID_24_Pos) ///< CAN identifier bit 24 481 #define CAN_TXID0_ID_25_Pos (4) 482 #define CAN_TXID0_ID_25 (0x01U << CAN_TXID0_ID_25_Pos) ///< CAN identifier bit 25 483 #define CAN_TXID0_ID_26_Pos (5) 484 #define CAN_TXID0_ID_26 (0x01U << CAN_TXID0_ID_26_Pos) ///< CAN identifier bit 26 485 #define CAN_TXID0_ID_27_Pos (6) 486 #define CAN_TXID0_ID_27 (0x01U << CAN_TXID0_ID_27_Pos) ///< CAN identifier bit 27 487 #define CAN_TXID0_ID_28_Pos (7) 488 #define CAN_TXID0_ID_28 (0x01U << CAN_TXID0_ID_28_Pos) ///< CAN identifier bit 28 489 490 //////////////////////////////////////////////////////////////////////////////// 491 /// @brief CAN_TXID1 register Bit definition 492 //////////////////////////////////////////////////////////////////////////////// 493 #define CAN_TXID1_ID_13_Pos (0) 494 #define CAN_TXID1_ID_13 (0x01U << CAN_TXID1_ID_13_Pos) ///< CAN identifier bit 13 495 #define CAN_TXID1_ID_14_Pos (1) 496 #define CAN_TXID1_ID_14 (0x01U << CAN_TXID1_ID_14_Pos) ///< CAN identifier bit 14 497 #define CAN_TXID1_ID_15_Pos (2) 498 #define CAN_TXID1_ID_15 (0x01U << CAN_TXID1_ID_15_Pos) ///< CAN identifier bit 15 499 #define CAN_TXID1_ID_16_Pos (3) 500 #define CAN_TXID1_ID_16 (0x01U << CAN_TXID1_ID_16_Pos) ///< CAN identifier bit 16 501 #define CAN_TXID1_ID_17_Pos (4) 502 #define CAN_TXID1_ID_17 (0x01U << CAN_TXID1_ID_17_Pos) ///< CAN identifier bit 17 503 #define CAN_TXID1_ID_18_Pos (5) 504 #define CAN_TXID1_ID_18 (0x01U << CAN_TXID1_ID_18_Pos) ///< CAN identifier bit 18 505 #define CAN_TXID1_ID_19_Pos (6) 506 #define CAN_TXID1_ID_19 (0x01U << CAN_TXID1_ID_19_Pos) ///< CAN identifier bit 19 507 #define CAN_TXID1_ID_20_Pos (7) 508 #define CAN_TXID1_ID_20 (0x01U << CAN_TXID1_ID_20_Pos) ///< CAN identifier bit 20 509 510 //////////////////////////////////////////////////////////////////////////////// 511 /// @brief CAN_TXDATAn register Bit definition 512 //////////////////////////////////////////////////////////////////////////////// 513 #define CAN_TXDATAn_Pos (0) 514 #define CAN_TXDATAn (0x00FFU << CAN_TXDATAn_Pos) ///< CAN transmit data n 515 516 //////////////////////////////////////////////////////////////////////////////// 517 /// @brief CAN_CDR register Bit definition 518 //////////////////////////////////////////////////////////////////////////////// 519 #define CAN_CDR_MODE_Pos (7) 520 #define CAN_CDR_MODE (0x01U << CAN_CDR_MODE_Pos) ///< CAN mode 521 522 523 524 /// @} 525 526 /// @} 527 528 /// @} 529 530 //////////////////////////////////////////////////////////////////////////////// 531 #endif 532 //////////////////////////////////////////////////////////////////////////////// 533