1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_dbg.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_DBG_H 22 #define __REG_DBG_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief DBG Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 48 #define DBG_BASE (0x40007080UL) ///< Base Address: 0x40007080 49 //////////////////////////////////////////////////////////////////////////////// 50 /// @brief DEBUG Registers Structure Definition 51 //////////////////////////////////////////////////////////////////////////////// 52 typedef struct { 53 __IO u32 IDCODE; ///< Code ID offset: 0x00 54 __IO u32 CR; ///< Control Register offset: 0x04 55 } DBGMCU_TypeDef; 56 57 58 59 //////////////////////////////////////////////////////////////////////////////// 60 /// @brief DBGMCU type pointer Definition 61 //////////////////////////////////////////////////////////////////////////////// 62 #define DBGMCU ((DBGMCU_TypeDef*) DBG_BASE) 63 64 65 66 //////////////////////////////////////////////////////////////////////////////// 67 /// @brief DBGMCU_IDCODE Register Bit Definition 68 //////////////////////////////////////////////////////////////////////////////// 69 #define DBGMCU_IDCODE_DEV_ID_Pos (0) 70 #define DBGMCU_IDCODE_DEV_ID (0xFFFFFFFFU << DBGMCU_IDCODE_DEV_ID_Pos) ///< Device identifier 71 72 //////////////////////////////////////////////////////////////////////////////// 73 /// @brief DBGMCU_CR Register Bit Definition 74 //////////////////////////////////////////////////////////////////////////////// 75 #define DBGMCU_CR_SLEEP_Pos (0) 76 #define DBGMCU_CR_SLEEP (0x01U << DBGMCU_CR_SLEEP_Pos) ///< Debug Sleep mode 77 #define DBGMCU_CR_STOP_Pos (1) 78 #define DBGMCU_CR_STOP (0x01U << DBGMCU_CR_STOP_Pos) ///< Debug Stop mode 79 #define DBGMCU_CR_STANDBY_Pos (2) 80 #define DBGMCU_CR_STANDBY (0x01U << DBGMCU_CR_STANDBY_Pos) ///< Debug Standby mode 81 #define DBGMCU_CR_TRACE_IOEN_Pos (5) 82 #define DBGMCU_CR_TRACE_IOEN (0x01U << DBGMCU_CR_TRACE_IOEN_Pos) ///< Trace pin assignment 83 #define DBGMCU_CR_TRACE_MODE_Pos (6) 84 #define DBGMCU_CR_TRACE_MODE_Msk (0x03U << DBGMCU_CR_TRACE_MODE_Pos) ///< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) 85 #define DBGMCU_CR_TRACE_MODE_0 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 0 86 #define DBGMCU_CR_TRACE_MODE_1 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< Bit 1 87 #define DBGMCU_CR_TRACE_MODE_ASYNC (0x00U << DBGMCU_CR_TRACE_MODE_Pos) ///< Tracking pin uses asynchronous mode 88 #define DBGMCU_CR_TRACE_MODE_SYNC1 (0x01U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 1 89 #define DBGMCU_CR_TRACE_MODE_SYNC2 (0x02U << DBGMCU_CR_TRACE_MODE_Pos) ///< The trace pin uses synchronous mode, and the data length is 2 90 91 #define DBGMCU_CR_IWDG_STOP_Pos (8) 92 #define DBGMCU_CR_IWDG_STOP (0x01U << DBGMCU_CR_IWDG_STOP_Pos) ///< Debug independent watchdog stopped when core is halted 93 #define DBGMCU_CR_WWDG_STOP_Pos (9) 94 #define DBGMCU_CR_WWDG_STOP (0x01U << DBGMCU_CR_WWDG_STOP_Pos) ///< Debug window watchdog stopped when core is halted 95 #define DBGMCU_CR_TIM_STOP_Pos (10) 96 #define DBGMCU_CR_TIM1_STOP (0x01U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM1 counter stopped when core is halted 97 #define DBGMCU_CR_TIM2_STOP (0x02U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM2 counter stopped when core is halted 98 #define DBGMCU_CR_TIM3_STOP (0x04U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM3 counter stopped when core is halted 99 #define DBGMCU_CR_TIM4_STOP (0x08U << DBGMCU_CR_TIM_STOP_Pos) ///< TIM4 counter stopped when core is halted 100 101 102 103 104 105 /// @} 106 107 /// @} 108 109 /// @} 110 111 //////////////////////////////////////////////////////////////////////////////// 112 #endif 113 //////////////////////////////////////////////////////////////////////////////// 114