1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_flash.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_FLASH_H 22 #define __REG_FLASH_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 //////////////////////////////////////////////////////////////////////////////// 39 /// @brief MM32 MCU Memory/Peripherals mapping 40 //////////////////////////////////////////////////////////////////////////////// 41 #define FLASH_BASE (0x08000000U) ///< FLASH base address in the alias region 42 #define SRAM_BASE (0x20000000U) ///< SRAM base address in the alias region 43 44 #define CACHE_BASE (APB2PERIPH_BASE + 0x6000) ///< Base Address: 0x40016000 45 46 //////////////////////////////////////////////////////////////////////////////// 47 /// @brief FLASH Base Address Definition 48 //////////////////////////////////////////////////////////////////////////////// 49 #define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000) ///< Base Address: 0x40022000 50 //////////////////////////////////////////////////////////////////////////////// 51 /// @brief OPTB Base Address Definition 52 //////////////////////////////////////////////////////////////////////////////// 53 #define OB_BASE (0x1FFFF800U) ///< Flash Option Bytes base address 54 #define PROTECT_BASE (0x1FFE0000U) ///< Flash Protect Bytes base address 55 56 57 58 //////////////////////////////////////////////////////////////////////////////// 59 /// @brief FLASH Registers Structure Definition 60 //////////////////////////////////////////////////////////////////////////////// 61 typedef struct { 62 __IO u32 ACR; ///< Access control Register offset: 0x00 63 __IO u32 KEYR; ///< Key Register offset: 0x04 64 __IO u32 OPTKEYR; ///< Option byte key Register offset: 0x08 65 __IO u32 SR; ///< State Register offset: 0x0C 66 __IO u32 CR; ///< Control Register offset: 0x10 67 __IO u32 AR; ///< Address Register offset: 0x14 68 __IO u32 RESERVED; 69 __IO u32 OBR; ///< Option bytes Register offset: 0x1C 70 __IO u32 WRPR; ///< Write protect Register offset: 0x20 71 } FLASH_TypeDef; 72 73 //////////////////////////////////////////////////////////////////////////////// 74 /// @brief OPT Structure Definition 75 //////////////////////////////////////////////////////////////////////////////// 76 typedef struct { 77 __IO u16 RDP; ///< Read Protect, offset: 0x00 78 __IO u16 USER; ///< User option byte, offset: 0x02 79 __IO u16 Data0; ///< User data 0, offset: 0x04 80 __IO u16 Data1; ///< User data 1, offset: 0x06 81 __IO u16 WRP0; ///< Flash write protection option byte 0, offset: 0x08 82 __IO u16 WRP1; ///< Flash write protection option byte 1, offset: 0x0A 83 __IO u16 WRP2; ///< Flash write protection option byte 2, offset: 0x0C 84 __IO u16 WRP3; ///< Flash write protection option byte 3, offset: 0x0E 85 } OB_TypeDef; 86 87 //////////////////////////////////////////////////////////////////////////////// 88 /// @brief PROTECT BYTES Structure Definition 89 //////////////////////////////////////////////////////////////////////////////// 90 typedef struct { 91 __IO u16 PROTECT_LEN0; ///< The length of Protect byte 0, offset: 0x00 92 __IO u16 PROTECT_ADDR0; ///< Data of Protect byte 0, offset: 0x02 93 __IO u16 PROTECT_LEN1; ///< The length of Protect byte 1, offset: 0x04 94 __IO u16 PROTECT_ADDR1; ///< Data of Protect byte 1, offset: 0x06 95 __IO u16 PROTECT_LEN2; ///< The length of Protect byte 2, offset: 0x08 96 __IO u16 PROTECT_ADDR2; ///< Data of Protect byte 2, offset: 0x0A 97 __IO u16 PROTECT_LEN3; ///< The length of Protect byte 3, offset: 0x0C 98 __IO u16 PROTECT_ADDR3; ///< Data of Protect byte 3, offset: 0x0E 99 } PROTECT_TypeDef; 100 //////////////////////////////////////////////////////////////////////////////// 101 /// @brief CACHE BYTES Structure Definition 102 //////////////////////////////////////////////////////////////////////////////// 103 104 typedef struct { 105 __IO u32 CCR; ///< Configuration and control register offset: 0x00 106 __IO u32 SR; ///< Status register offset: 0x04 107 __IO u32 IMR; ///< Interrupt mask register offset: 0x08 108 __IO u32 ISR; ///< Interrupt status register offset: 0x0C 109 __IO u32 RESERVED0; ///< offset: 0x10 110 __IO u32 CSHR; ///< Hit Statistics Register offset: 0x14 111 __IO u32 CSMR; ///< Lost Statistics Register offset: 0x18 112 } CACHE_TypeDef; 113 114 //////////////////////////////////////////////////////////////////////////////// 115 /// @brief FLASH type pointer Definition 116 //////////////////////////////////////////////////////////////////////////////// 117 #define FLASH ((FLASH_TypeDef*) FLASH_REG_BASE) 118 //////////////////////////////////////////////////////////////////////////////// 119 /// @brief OPTB type pointer Definition 120 //////////////////////////////////////////////////////////////////////////////// 121 #define OB ((OB_TypeDef*) OB_BASE) 122 #define PROTECT ((PROTECT_TypeDef*) PROTECT_BASE) 123 //////////////////////////////////////////////////////////////////////////////// 124 /// @brief CACHE pointer Definition 125 //////////////////////////////////////////////////////////////////////////////// 126 #define CACHE ((CACHE_TypeDef*) CACHE_BASE) 127 //////////////////////////////////////////////////////////////////////////////// 128 /// @brief FLASH_ACR Register Bit Definition 129 //////////////////////////////////////////////////////////////////////////////// 130 #define FLASH_ACR_LATENCY_Pos (0) 131 #define FLASH_ACR_LATENCY (0x07U << FLASH_ACR_LATENCY_Pos) ///< LATENCY[2:0] bits (Latency) 132 #define FLASH_ACR_LATENCY_0 (0x00U << FLASH_ACR_LATENCY_Pos) ///< 0 waiting state 133 #define FLASH_ACR_LATENCY_1 (0x01U << FLASH_ACR_LATENCY_Pos) ///< 1 waiting state 134 #define FLASH_ACR_LATENCY_2 (0x02U << FLASH_ACR_LATENCY_Pos) ///< 2 waiting state 135 #define FLASH_ACR_LATENCY_3 (0x03U << FLASH_ACR_LATENCY_Pos) ///< 3 waiting state 136 #define FLASH_ACR_HLFCYA_Pos (3) 137 #define FLASH_ACR_HLFCYA (0x01U << FLASH_ACR_HLFCYA_Pos) ///< Flash Half Cycle Access Enable 138 #define FLASH_ACR_PRFTBE_Pos (4) 139 #define FLASH_ACR_PRFTBE (0x01U << FLASH_ACR_PRFTBE_Pos) ///< Prefetch Buffer Enable 140 #define FLASH_ACR_PRFTBS_Pos (5) 141 #define FLASH_ACR_PRFTBS (0x01U << FLASH_ACR_PRFTBS_Pos) ///< Prefetch Buffer Status 142 //////////////////////////////////////////////////////////////////////////////// 143 /// @brief FLASH_KEYR Register Bit Definition 144 //////////////////////////////////////////////////////////////////////////////// 145 #define FLASH_KEYR_FKEY_Pos (0) 146 #define FLASH_KEYR_FKEY (0xFFFFFFFFU << FLASH_KEYR_FKEY_Pos) ///< FLASH Key 147 148 //////////////////////////////////////////////////////////////////////////////// 149 /// @brief FLASH_OPTKEYR Register Bit Definition 150 //////////////////////////////////////////////////////////////////////////////// 151 #define FLASH_OPTKEYR_OPTKEY_Pos (0) 152 #define FLASH_OPTKEYR_OPTKEY (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEY_Pos) ///< Option Byte Key 153 154 //////////////////////////////////////////////////////////////////////////////// 155 /// @brief FLASH_SR Register Bit Definition 156 //////////////////////////////////////////////////////////////////////////////// 157 #define FLASH_SR_BUSY_Pos (0) 158 #define FLASH_SR_BUSY (0x01U << FLASH_SR_BUSY_Pos) ///< Busy 159 #define FLASH_SR_PGERR_Pos (2) 160 #define FLASH_SR_PGERR (0x01U << FLASH_SR_PGERR_Pos) ///< Programming Error 161 #define FLASH_SR_WRPRTERR_Pos (4) 162 #define FLASH_SR_WRPRTERR (0x01U << FLASH_SR_WRPRTERR_Pos) ///< Write Protection Error 163 #define FLASH_SR_EOP_Pos (5) 164 #define FLASH_SR_EOP (0x01U << FLASH_SR_EOP_Pos) ///< End of operation 165 166 //////////////////////////////////////////////////////////////////////////////// 167 /// @brief FLASH_CR Register Bit Definition 168 //////////////////////////////////////////////////////////////////////////////// 169 #define FLASH_CR_PG_Pos (0) 170 #define FLASH_CR_PG (0x01U << FLASH_CR_PG_Pos) ///< Programming 171 #define FLASH_CR_PER_Pos (1) 172 #define FLASH_CR_PER (0x01U << FLASH_CR_PER_Pos) ///< Page Erase 173 #define FLASH_CR_MER_Pos (2) 174 #define FLASH_CR_MER (0x01U << FLASH_CR_MER_Pos) ///< Mass Erase 175 #define FLASH_CR_OPTPG_Pos (4) 176 #define FLASH_CR_OPTPG (0x01U << FLASH_CR_OPTPG_Pos) ///< Option Byte Programming 177 #define FLASH_CR_OPTER_Pos (5) 178 #define FLASH_CR_OPTER (0x01U << FLASH_CR_OPTER_Pos) ///< Option Byte Erase 179 #define FLASH_CR_STRT_Pos (6) 180 #define FLASH_CR_STRT (0x01U << FLASH_CR_STRT_Pos) ///< Start 181 #define FLASH_CR_LOCK_Pos (7) 182 #define FLASH_CR_LOCK (0x01U << FLASH_CR_LOCK_Pos) ///< Lock 183 #define FLASH_CR_OPTWRE_Pos (9) 184 #define FLASH_CR_OPTWRE (0x01U << FLASH_CR_OPTWRE_Pos) ///< Option Bytes Write Enable 185 #define FLASH_CR_ERRIE_Pos (10) 186 #define FLASH_CR_ERRIE (0x01U << FLASH_CR_ERRIE_Pos) ///< Error Interrupt Enable 187 #define FLASH_CR_EOPIE_Pos (12) 188 #define FLASH_CR_EOPIE (0x01U << FLASH_CR_EOPIE_Pos) ///< End of operation interrupt enable 189 190 //////////////////////////////////////////////////////////////////////////////// 191 /// @brief FLASH_AR Register Bit Definition 192 //////////////////////////////////////////////////////////////////////////////// 193 #define FLASH_AR_FAR_Pos (0) 194 #define FLASH_AR_FAR (0xFFFFFFFFU << FLASH_AR_FAR_Pos) ///< Flash Address 195 196 //////////////////////////////////////////////////////////////////////////////// 197 /// @brief FLASH_OBR Register Bit Definition 198 //////////////////////////////////////////////////////////////////////////////// 199 #define FLASH_OBR_OPTERR_Pos (0) 200 #define FLASH_OBR_OPTERR (0x01U << FLASH_OBR_OPTERR_Pos) ///< Option Byte Error 201 #define FLASH_OBR_RDPRT_Pos (1) 202 #define FLASH_OBR_RDPRT (0x01U << FLASH_OBR_RDPRT_Pos) ///< Read protection level status 203 #define FLASH_OBR_USER_Pos (2) 204 #define FLASH_OBR_USER (0xFFU << FLASH_OBR_USER_Pos) ///< User Option Bytes 205 206 #define FLASH_OBR_WDG_SW (0x01U << FLASH_OBR_USER_Pos) ///< WDG_SW 207 #define FLASH_OBR_RST_STOP (0x02U << FLASH_OBR_USER_Pos) ///< nRST_STOP 208 #define FLASH_OBR_RST_STDBY (0x04U << FLASH_OBR_USER_Pos) ///< nRST_STDBY 209 210 211 #define FLASH_OBR_Data0_Pos (10) 212 #define FLASH_OBR_Data0 (0xFFU << FLASH_OBR_Data0_Pos) ///< User data storage option byte 213 #define FLASH_OBR_Data1_Pos (18) 214 #define FLASH_OBR_Data1 (0xFFU << FLASH_OBR_Data1_Pos) ///< User data storage option byte 215 216 //////////////////////////////////////////////////////////////////////////////// 217 /// @brief FLASH_WRPR Register Bit Definition 218 //////////////////////////////////////////////////////////////////////////////// 219 #define FLASH_WRPR_WRP_Pos (0) 220 #define FLASH_WRPR_WRP (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) ///< Write Protect 221 222 223 224 //////////////////////////////////////////////////////////////////////////////// 225 /// @brief CACHE_CCR Register Bit Definition 226 //////////////////////////////////////////////////////////////////////////////// 227 #define CACHE_CCR_EN_Pos (0) 228 #define CACHE_CCR_EN (0x01U << CACHE_CCR_EN_Pos) ///< Cache Enable 229 #define CACHE_CCR_INV_Pos (1) 230 #define CACHE_CCR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Manually invalidate the request 231 #define CACHE_CCR_POW_Pos (2) 232 #define CACHE_CCR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< Manual SRAM power request 233 #define CACHE_CCR_MAN_POW_Pos (3) 234 #define CACHE_CCR_MAN_POW (0x01U << CACHE_CCR_MAN_POW_Pos) ///< Set manual or automatic SRAM power request 235 #define CACHE_CCR_MAN_INV_Pos (4) 236 #define CACHE_CCR_MAN_INV (0x01U << CACHE_CCR_MAN_INV_Pos) ///< Manually or automatically disable it 237 #define CACHE_CCR_PREFETCH_Pos (5) 238 #define CACHE_CCR_PREFETCH (0x01U << CACHE_CCR_PREFETCH_Pos) ///< Prefetch function 239 #define CACHE_CCR_STATISTIC_Pos (6) 240 #define CACHE_CCR_STATISTIC (0x01U << CACHE_CCR_STATISTIC_Pos) ///< Statistics enable 241 //////////////////////////////////////////////////////////////////////////////// 242 /// @brief CACHE_SR Register Bit Definition 243 //////////////////////////////////////////////////////////////////////////////// 244 #define CACHE_SR_CS_Pos (0) 245 #define CACHE_SR_CS0 (0x00U << CACHE_CCR_CS_Pos) ///< Cache is disabled 246 #define CACHE_SR_CS1 (0x01U << CACHE_CCR_CS_Pos) ///< Cache is being enabled 247 #define CACHE_SR_CS2 (0x02U << CACHE_CCR_CS_Pos) ///< Cache is enabled 248 #define CACHE_SR_CS3 (0x03U << CACHE_CCR_CS_Pos) ///< Cache is being disabled 249 #define CACHE_SR_INV_Pos (2) 250 #define CACHE_SR_INV (0x01U << CACHE_CCR_INV_REQ_Pos) ///< Invalidation status 251 #define CACHE_SR_POW_Pos (4) 252 #define CACHE_SR_POW (0x01U << CACHE_CCR_POW_REQ_Pos) ///< SRAM power response 253 //////////////////////////////////////////////////////////////////////////////// 254 /// @brief CACHE_IMR Register Bit Definition 255 //////////////////////////////////////////////////////////////////////////////// 256 #define CACHE_IMR_MAN_INV_Pos (0) 257 #define CACHE_IMR_MAN_INV (0x01U << CACHE_IMR_MAN_INV_Pos) ///< Mask the interrupt request of manual invalidation error 258 #define CACHE_IMR_POW_Pos (1) 259 #define CACHE_IMR_POW (0x01U << CACHE_IMR_POW_Pos) ///< Mask the interrupt request of power supply error 260 //////////////////////////////////////////////////////////////////////////////// 261 /// @brief CACHE_ISR Register Bit Definition 262 //////////////////////////////////////////////////////////////////////////////// 263 #define CACHE_ISR_MAN_INV_Pos (0) 264 #define CACHE_ISR_MAN_INV (0x01U << CACHE_ISR_MAN_INV_Pos) ///< Manual invalidation of error flags 265 #define CACHE_ISR_POW_Pos (1) 266 #define CACHE_ISR_POW (0x01U << CACHE_ISR_POW_Pos) ///< SRAM power error flags 267 //////////////////////////////////////////////////////////////////////////////// 268 /// @brief CACHE_CSHR Register Bit Definition 269 //////////////////////////////////////////////////////////////////////////////// 270 #define CACHE_CSHR (0xFFFFU ) ///< Cache Hits 271 //////////////////////////////////////////////////////////////////////////////// 272 /// @brief CACHE_CSHR Register Bit Definition 273 //////////////////////////////////////////////////////////////////////////////// 274 #define CACHE_CSMR (0xFFFFU ) ///< Cache Lost times 275 276 277 278 279 280 281 282 /// @} 283 284 /// @} 285 286 /// @} 287 288 //////////////////////////////////////////////////////////////////////////////// 289 #endif 290 //////////////////////////////////////////////////////////////////////////////// 291