1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_rtc.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_RTC_H 22 #define __REG_RTC_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 //////////////////////////////////////////////////////////////////////////////// 45 /// @brief RTC Base Address Definition 46 //////////////////////////////////////////////////////////////////////////////// 47 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) ///< Base Address: 0x40002800 48 49 50 51 52 53 //////////////////////////////////////////////////////////////////////////////// 54 /// @brief RTC Registers Structure Definition 55 //////////////////////////////////////////////////////////////////////////////// 56 typedef struct { 57 union { 58 __IO u32 CR; ///< Control Register, offset: 0x00 59 __IO u32 CRH; 60 }; 61 union { 62 __IO u32 CSR; ///< Control & Status Register, offset: 0x04 63 __IO u32 CRL; 64 }; 65 __IO u32 PRLH; ///< Prescaler Reload Value High, offset: 0x08 66 __IO u32 PRLL; ///< Prescaler Reload Value Low, offset: 0x0C 67 __IO u32 DIVH; ///< Clock Divider High, offset: 0x10 68 __IO u32 DIVL; ///< Clock Divider Low, offset: 0x14 69 __IO u32 CNTH; ///< Counter High, offset: 0x18 70 __IO u32 CNTL; ///< Counter Low, offset: 0x1C 71 __IO u32 ALRH; ///< Alarm High, offset: 0x20 72 __IO u32 ALRL; ///< Alarm Low, offset: 0x24 73 __IO u32 MSRH; ///< Millisecond alarm high register offset: 0x28 74 __IO u32 MSRL; ///< Millisecond alarm low register offset: 0x2C 75 __IO u32 RESERVED0; ///< Reserved offset: 0x30 76 __IO u32 RESERVED1; ///< Reserved offset: 0x34 77 __IO u32 RESERVED2; ///< Reserved offset: 0x38 78 __IO u32 LSE_CFG; ///< LSE configure register offset: 0x3C 79 } RTC_TypeDef; 80 81 82 //////////////////////////////////////////////////////////////////////////////// 83 /// @brief RTC type pointer Definition 84 //////////////////////////////////////////////////////////////////////////////// 85 #define RTC ((RTC_TypeDef*)RTC_BASE) 86 87 88 89 //////////////////////////////////////////////////////////////////////////////// 90 /// @brief RTC_CR Register Bit Definition 91 //////////////////////////////////////////////////////////////////////////////// 92 #define RTC_CR_SECIE_Pos (0) 93 #define RTC_CR_SECIE (0x01U << RTC_CR_SECIE_Pos) ///< Second Interrupt Enable 94 #define RTC_CR_ALRIE_Pos (1) 95 #define RTC_CR_ALRIE (0x01U << RTC_CR_ALRIE_Pos) ///< Alarm Interrupt Enable 96 #define RTC_CR_OWIE_Pos (2) 97 #define RTC_CR_OWIE (0x01U << RTC_CR_OWIE_Pos) ///< OverfloW Interrupt Enable 98 99 //////////////////////////////////////////////////////////////////////////////// 100 /// @brief RTC_CSR Register Bit Definition 101 //////////////////////////////////////////////////////////////////////////////// 102 #define RTC_CSR_SECF_Pos (0) 103 #define RTC_CSR_SECF (0x01 << RTC_CSR_SECF_Pos) ///< Second Flag 104 #define RTC_CSR_ALRF_Pos (1) 105 #define RTC_CSR_ALRF (0x01 << RTC_CSR_ALRF_Pos) ///< Alarm Flag 106 #define RTC_CSR_OWF_Pos (2) 107 #define RTC_CSR_OWF (0x01 << RTC_CSR_OWF_Pos) ///< OverfloW Flag 108 #define RTC_CSR_RSF_Pos (3) 109 #define RTC_CSR_RSF (0x01 << RTC_CSR_RSF_Pos) ///< Registers Synchronized Flag 110 #define RTC_CSR_CNF_Pos (4) 111 #define RTC_CSR_CNF (0x01 << RTC_CSR_CNF_Pos) ///< Configuration Flag 112 #define RTC_CSR_RTOFF_Pos (5) 113 #define RTC_CSR_RTOFF (0x01 << RTC_CSR_RTOFF_Pos) ///< RTC operation OFF 114 #define RTC_CSR_ALPEN_Pos (6) 115 #define RTC_CSR_ALPEN (0x01 << RTC_CSR_ALPEN_Pos) ///< RTC Alarm Loop Enable 116 //////////////////////////////////////////////////////////////////////////////// 117 /// @brief RTC_PRLH Register Bit Definition 118 //////////////////////////////////////////////////////////////////////////////// 119 #define RTC_PRLH_PRL_Pos (0) 120 #define RTC_PRLH_PRL (0x0F << RTC_PRLH_PRL_Pos) ///< RTC Prescaler Reload Value High 121 122 //////////////////////////////////////////////////////////////////////////////// 123 /// @brief RTC_PRLL Register Bit Definition 124 //////////////////////////////////////////////////////////////////////////////// 125 #define RTC_PRLL_PRL_Pos (0) 126 #define RTC_PRLL_PRL (0xFFFFU << RTC_PRLL_PRL_Pos) ///< RTC Prescaler Reload Value Low 127 128 //////////////////////////////////////////////////////////////////////////////// 129 /// @brief RTC_DIVH Register Bit Definition 130 //////////////////////////////////////////////////////////////////////////////// 131 #define RTC_DIVH_DIV_Pos (0) 132 #define RTC_DIVH_DIV (0x0F << RTC_DIVH_DIV_Pos) ///< RTC Clock Divider High 133 134 //////////////////////////////////////////////////////////////////////////////// 135 /// @brief RTC_DIVL Register Bit Definition 136 //////////////////////////////////////////////////////////////////////////////// 137 #define RTC_DIVL_DIV_Pos (0) 138 #define RTC_DIVL_DIV (0xFFFFU << RTC_DIVL_DIV_Pos) ///< RTC Clock Divider Low 139 140 //////////////////////////////////////////////////////////////////////////////// 141 /// @brief RTC_CNTH Register Bit Definition 142 //////////////////////////////////////////////////////////////////////////////// 143 #define RTC_CNTH_CNT_Pos (0) 144 #define RTC_CNTH_CNT (0xFFFFU << RTC_CNTH_CNT_Pos) ///< RTC Counter High 145 146 //////////////////////////////////////////////////////////////////////////////// 147 /// @brief RTC_CNTL Register Bit Definition 148 //////////////////////////////////////////////////////////////////////////////// 149 #define RTC_CNTL_CNT_Pos (0) 150 #define RTC_CNTL_CNT (0xFFFFU << RTC_CNTL_CNT_Pos) ///< RTC Counter Low 151 152 //////////////////////////////////////////////////////////////////////////////// 153 /// @brief RTC_ALRH Register Bit Definition 154 //////////////////////////////////////////////////////////////////////////////// 155 #define RTC_ALRH_ALR_Pos (0) 156 #define RTC_ALRH_ALR (0xFFFFU << RTC_ALRH_ALR_Pos) ///< RTC Alarm High 157 158 //////////////////////////////////////////////////////////////////////////////// 159 /// @brief RTC_ALRL Register Bit Definition 160 //////////////////////////////////////////////////////////////////////////////// 161 #define RTC_ALRL_ALR_Pos (0) 162 #define RTC_ALRL_ALR (0xFFFFU << RTC_ALRL_ALR_Pos) ///< RTC Alarm Low 163 164 165 //////////////////////////////////////////////////////////////////////////////// 166 /// @brief RTC_MSRH Register Bit Definition 167 //////////////////////////////////////////////////////////////////////////////// 168 #define RTC_MSRH_MSR_Pos (0) 169 #define RTC_MSRH_MSR (0xFFFFU << RTC_MSRH_MSR_Pos) ///< RTC MS Alarm Register High 170 171 172 //////////////////////////////////////////////////////////////////////////////// 173 /// @brief RTC_MSRL Register Bit Definition 174 //////////////////////////////////////////////////////////////////////////////// 175 #define RTC_MSRL_MSR_Pos (0) 176 #define RTC_MSRL_MSR (0xFFFFU << RTC_MSRL_MSR_Pos) ///< RTC MS Alarm Register Low 177 178 //////////////////////////////////////////////////////////////////////////////// 179 /// @brief RTC_LSE_CFG Register Bit Definition 180 //////////////////////////////////////////////////////////////////////////////// 181 182 #define RTC_LSE_CFG_TEST_Pos (0) 183 #define RTC_LSE_CFG_TEST (0x0FU << RTC_LSE_CFG_TEST_Pos) ///< Test control signal 184 #define RTC_LSE_CFG_DR_Pos (4) 185 #define RTC_LSE_CFG_DR (0x03U << RTC_LSE_CFG_DR_Pos) ///< Drive capability selection 186 #define RTC_LSE_CFG_RFB_SEL_Pos (6) 187 #define RTC_LSE_CFG_RFB_SEL_3 (0x03U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 3M 188 #define RTC_LSE_CFG_RFB_SEL_6 (0x02U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 6M 189 #define RTC_LSE_CFG_RFB_SEL_10 (0x01U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 10M 190 #define RTC_LSE_CFG_RFB_SEL_12 (0x00U << RTC_LSE_CFG_RFB_SEL_Pos) ///< Feedback resistance selection 12M 191 #define RTC_LSE_CFG_IB_Pos (8) 192 #define RTC_LSE_CFG_IB (0x01U << RTC_MSRL_MSR_Pos) ///< Bias current regulation 193 194 195 /// @} 196 197 /// @} 198 199 /// @} 200 201 //////////////////////////////////////////////////////////////////////////////// 202 #endif 203 //////////////////////////////////////////////////////////////////////////////// 204