1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_sdio.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_SDIO_H 22 #define __REG_SDIO_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 //#include "types.h" 29 #include "mm32_reg.h" 30 31 //#if defined ( __CC_ARM ) 32 //#pragma anon_unions 33 //#endif 34 35 36 //////////////////////////////////////////////////////////////////////////////// 37 /// @brief SDIO Base Address Definition 38 //////////////////////////////////////////////////////////////////////////////// 39 #define SDIO_BASE (0x40018000U) ///< Base Address: 0x40018000 40 41 42 //////////////////////////////////////////////////////////////////////////////// 43 /// @brief SDIO Register Structure Definition 44 //////////////////////////////////////////////////////////////////////////////// 45 46 typedef struct { 47 __IO u32 MMC_CTRL; ///< SDIO transmit data register, offset: 0x00 48 __IO u32 MMC_IO; ///< SDIO receive data register, offset: 0x04 49 __IO u32 MMC_BYTECNTL; ///< SDIO current state register, offset: 0x08 50 __IO u32 MMC_TR_BLOCKCNT; ///< SDIO interruput state register, offset: 0x0C 51 __IO u32 MMC_CRCCTL; ///< SDIO interruput enable register, offset: 0x10 52 __IO u32 CMD_CRC; ///< SDIO interruput control register, offset: 0x14 53 __IO u32 DAT_CRCL; ///< SDIO global control register, offset: 0x18 54 __IO u32 DAT_CRCH; ///< SDIO common control register, offset: 0x1C 55 __IO u32 MMC_PORT; ///< SDIO baud rate control register, offset: 0x20 56 __IO u32 MMC_INT_MASK; ///< SDIO receive data number register, offset: 0x24 57 __IO u32 CLR_MMC_INT; ///< SDIO chip select register, offset: 0x28 58 __IO u32 MMC_CARDSEL; ///< SDIO extand control register, offset: 0x2C 59 __IO u32 MMC_SIG; ///< 0ffset: 0x30 60 __IO u32 MMC_IO_MBCTL; ///< 0ffset: 0x34 61 __IO u32 MMC_BLOCKCNT; ///< 0ffset: 0x38 62 __IO u32 MMC_TIMEOUTCNT; ///< 0ffset: 0x3C 63 __IO u32 CMD_BUF0; ///< 0ffset: 0x40 64 __IO u32 CMD_BUF1; ///< 0ffset: 0x44 65 __IO u32 CMD_BUF2; ///< 0ffset: 0x48 66 __IO u32 CMD_BUF3; ///< 0ffset: 0x4C 67 __IO u32 CMD_BUF4; ///< 0ffset: 0x50 68 __IO u32 CMD_BUF5; ///< 0ffset: 0x54 69 __IO u32 CMD_BUF6; ///< 0ffset: 0x58 70 __IO u32 CMD_BUF7; ///< 0ffset: 0x5C 71 __IO u32 CMD_BUF8; ///< 0ffset: 0x60 72 __IO u32 CMD_BUF9; ///< 0ffset: 0x64 73 __IO u32 CMD_BUF10; ///< 0ffset: 0x68 74 __IO u32 CMD_BUF11; ///< 0ffset: 0x6C 75 __IO u32 CMD_BUF12; ///< 0ffset: 0x70 76 __IO u32 CMD_BUF13; ///< 0ffset: 0x74 77 __IO u32 CMD_BUF14; ///< 0ffset: 0x78 78 __IO u32 CMD_BUF15; ///< 0ffset: 0x7C 79 __IO u32 BUF_CTL; ///< 0ffset: 0x80 80 81 __IO u32 RESERVED[31]; ///< 0ffset: 0x84 82 union { 83 __IO u32 DATA_BUF0; ///< 0ffset: 0x100 84 __IO u32 FIFO; 85 }; 86 __IO u32 DATA_BUF1; ///< 0ffset: 0x104 87 __IO u32 DATA_BUF2; ///< 0ffset: 0x108 88 __IO u32 DATA_BUF3; ///< 0ffset: 0x10C 89 __IO u32 DATA_BUF4; ///< 0ffset: 0x110 90 } SDIO_TypeDef; 91 92 //////////////////////////////////////////////////////////////////////////////// 93 /// @brief SDIO type pointer Definition 94 //////////////////////////////////////////////////////////////////////////////// 95 #define SDIO ((SDIO_TypeDef*) SDIO_BASE) 96 97 //////////////////////////////////////////////////////////////////////////////// 98 /// @brief SDIO_MMC_CTRL Register Bit Definition 99 //////////////////////////////////////////////////////////////////////////////// 100 #define SDIO_MMC_CTRL_OPMSel_Pos (0) 101 #define SDIO_MMC_CTRL_OPMSel (0x01U << SDIO_MMC_CTRL_OPMSel_Pos) ///< SD/MMC/SDIO port operation mode select 102 #define SDIO_MMC_CTRL_SelSM_Pos (1) 103 #define SDIO_MMC_CTRL_SelSM (0x01U << SDIO_MMC_CTRL_SelSM_Pos) ///< Select automatic mode 104 #define SDIO_MMC_CTRL_OUTM_Pos (2) 105 #define SDIO_MMC_CTRL_OUTM (0x01U << SDIO_MMC_CTRL_OUTM_Pos) ///< SD/MMC/SDIO port CMD line output driver mode selection Open drain 106 #define SDIO_MMC_CTRL_CLKSP_Pos (3) 107 #define SDIO_MMC_CTRL_CLKSP2 (0x00U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/2 baseclock 108 #define SDIO_MMC_CTRL_CLKSP4 (0x01U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/4 baseclock 109 #define SDIO_MMC_CTRL_CLKSP6 (0x02U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/6 baseclock 110 #define SDIO_MMC_CTRL_CLKSP8 (0x03U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/8 baseclock 111 #define SDIO_MMC_CTRL_CLKSP10 (0x04U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/10 baseclock 112 #define SDIO_MMC_CTRL_CLKSP12 (0x05U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/12 baseclock 113 #define SDIO_MMC_CTRL_CLKSP14 (0x06U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/14 baseclock 114 #define SDIO_MMC_CTRL_CLKSP16 (0x07U << SDIO_MMC_CTRL_CLKSP_Pos) ///< SD/MMC/SDIO port CLK linespeedselection 1/16 baseclock 115 #define SDIO_MMC_CTRL_SelPTSM_Pos (6) 116 #define SDIO_MMC_CTRL_SelPTSM (0x01U << SDIO_MMC_CTRL_SelPTSM_Pos) ///< SelectSD/MMC/SDIO port transfer high speed mode 117 #define SDIO_MMC_CTRL_DATWT_Pos (7) 118 #define SDIO_MMC_CTRL_DATWT (0x01U << SDIO_MMC_CTRL_DATWT_Pos) ///< Definethe bus width of SD/MMC/SDIO port DAT line 119 #define SDIO_MMC_CTRL_MDEN_Pos (8) 120 #define SDIO_MMC_CTRL_MDEN (0x01U << SDIO_MMC_CTRL_MDEN_Pos) ///< SDIO mode enable 121 #define SDIO_MMC_CTRL_INTEN_Pos (9) 122 #define SDIO_MMC_CTRL_INTEN (0x01U << SDIO_MMC_CTRL_INTEN_Pos) ///< SDIO interrupt enale signal 123 #define SDIO_MMC_CTRL_RDWTEN_Pos (10) 124 #define SDIO_MMC_CTRL_RDWTEN (0x01U << SDIO_MMC_CTRL_RDWTEN_Pos) ///< SDIO read wait enable signal 125 //////////////////////////////////////////////////////////////////////////////// 126 /// @brief SDIO_MMC_IO Register Bit Definition 127 //////////////////////////////////////////////////////////////////////////////// 128 #define SDIO_MMC_IO_AUTODATTR_Pos (0) 129 #define SDIO_MMC_IO_AUTODATTR (0x01U << SDIO_MMC_IO_AUTODATTR_Pos) ///< Set up automatic data transfer 130 #define SDIO_MMC_IO_TRANSFDIR_Pos (1) 131 #define SDIO_MMC_IO_TRANSFDIR (0x01U << SDIO_MMC_IO_TRANSFDIR_Pos) ///< Set the direction of data transfer 132 #define SDIO_MMC_IO_AUTOTR_Pos (2) 133 #define SDIO_MMC_IO_AUTOTR (0x01U << SDIO_MMC_IO_AUTOTR_Pos) ///< Set up automatic 8-bit/command/response transmission. 134 #define SDIO_MMC_IO_RESPCMDSEL_Pos (3) 135 #define SDIO_MMC_IO_RESPCMDSEL (0x01U << SDIO_MMC_IO_RESPCMDSEL_Pos) ///< Receive response 136 #define SDIO_MMC_IO_CID_CSDRD_Pos (4) 137 #define SDIO_MMC_IO_CID_CSDRD (0x01U << SDIO_MMC_IO_CID_CSDRD_Pos) ///< CID and CSD reads 138 #define SDIO_MMC_IO_PCLKG_Pos (5) 139 #define SDIO_MMC_IO_PCLKG (0x01U << SDIO_MMC_IO_PCLKG_Pos) ///< SD/MMC/SDIO port CLK line 8 empty clock generated 140 #define SDIO_MMC_IO_ENRRESP_Pos (6) 141 #define SDIO_MMC_IO_ENRRESP (0x01U << SDIO_MMC_IO_ENRRESP_Pos) ///< Enable automatic receiving of responses after a command 142 #define SDIO_MMC_IO_AUTOCLKG_Pos (7) 143 #define SDIO_MMC_IO_AUTOCLKG (0x01U << SDIO_MMC_IO_AUTOCLKG_Pos) ///< Enable automatic conversion of the 8 empty clock after a response/command or a single block of data 144 #define SDIO_MMC_IO_CMDCH_Pos (8) 145 #define SDIO_MMC_IO_CMDCH (0x01U << SDIO_MMC_IO_CMDCH_Pos) ///< SDIO mode enable 146 #define SDIO_MMC_IO_CMDAF_Pos (9) 147 #define SDIO_MMC_IO_CMDAF (0x01U << SDIO_MMC_IO_CMDAF_Pos) ///< SDIO CMD12 / IO abort flag 148 //////////////////////////////////////////////////////////////////////////////// 149 /// @brief SDIO_MMC_BYTECNTL Register Bit Definition 150 //////////////////////////////////////////////////////////////////////////////// 151 #define SDIO_MMC_BYTECNTL_CNT (0xFFFFU) ///< Data transfer byte count register 152 //////////////////////////////////////////////////////////////////////////////// 153 /// @brief SDIO_MMC_TR_BLOCKCNT Register Bit Definition 154 //////////////////////////////////////////////////////////////////////////////// 155 #define SDIO_MMC_TR_BLOCKCNT_CNT (0xFFFFU) ///< The value of the counter that completes the transfer when multiple blocks are transferred. 156 //////////////////////////////////////////////////////////////////////////////// 157 /// @brief SDIO_MMC_CRCCTL Register Bit Definition 158 //////////////////////////////////////////////////////////////////////////////// 159 #define SDIO_MMC_CRCCTL_DAT_CRCE_Pos (0) 160 #define SDIO_MMC_CRCCTL_DAT_CRCE (0x01U << SDIO_MMC_CRCCTL_DAT_CRCE_Pos) ///< DAT CRC error 161 #define SDIO_MMC_CRCCTL_CMD_CRCE_Pos (1) 162 #define SDIO_MMC_CRCCTL_CMD_CRCE (0x01U << SDIO_MMC_CRCCTL_CMD_CRCE_Pos) ///< CMD CRC error 163 #define SDIO_MMC_CRCCTL_DAT_CRCS_Pos (2) 164 #define SDIO_MMC_CRCCTL_DAT_CRCS (0x03U << SDIO_MMC_CRCCTL_DAT_CRCS_Pos) ///< DAT CRC selection 165 #define SDIO_MMC_CRCCTL_ENRDMB_Pos (4) 166 #define SDIO_MMC_CRCCTL_ENRDMB (0x01U << SDIO_MMC_CRCCTL_ENRDMB_Pos) ///< Enable reading multiple blocks of data before responding 167 #define SDIO_MMC_CRCCTL_ENCHK_Pos (5) 168 #define SDIO_MMC_CRCCTL_ENCHK (0x01U << SDIO_MMC_CRCCTL_ENCHK_Pos) ///< Enable automatic checking 169 #define SDIO_MMC_CRCCTL_DAT_CRCEN_Pos (6) 170 #define SDIO_MMC_CRCCTL_DAT_CRCEN (0x01U << SDIO_MMC_CRCCTL_DAT_CRCEN_Pos) ///< SD/MMC/SDIO PORT DAT line CRC circuit enablement 171 #define SDIO_MMC_CRCCTL_CMD_CRCEN_Pos (7) 172 #define SDIO_MMC_CRCCTL_CMD_CRCEN (0x01U << SDIO_MMC_CRCCTL_CMD_CRCEN_Pos) ///< SD/MMC/SDIO port CMD line CRC circuit enablement 173 //////////////////////////////////////////////////////////////////////////////// 174 /// @brief SDIO_CMD_CRC Register Bit Definition 175 //////////////////////////////////////////////////////////////////////////////// 176 #define SDIO_CMD_CRC_CMD_CRCV (0x7FU) ///< CMD_CRCV register value 177 //////////////////////////////////////////////////////////////////////////////// 178 /// @brief SDIO_DAT_CRCL Register Bit Definition 179 //////////////////////////////////////////////////////////////////////////////// 180 #define SDIO_DAT_CRCL_DAT_CRCLV (0xFFU) ///< CMD_CRCV low register value 181 //////////////////////////////////////////////////////////////////////////////// 182 /// @brief SDIO_DAT_CRCH Register Bit Definition 183 //////////////////////////////////////////////////////////////////////////////// 184 #define SDIO_DAT_CRCL_DAT_CRCHV (0xFFU) ///< CMD_CRCV high register value 185 //////////////////////////////////////////////////////////////////////////////// 186 /// @brief SDIO_MMC_PORT Register Bit Definition 187 //////////////////////////////////////////////////////////////////////////////// 188 #define SDIO_MMC_PORT_NTCR_Pos (0) 189 #define SDIO_MMC_PORT_NTCR (0x0FU << SDIO_MMC_PORT_NTCR_Pos) ///< Ncr timeout count register 190 #define SDIO_MMC_PORT_AUTONTEN_Pos (4) 191 #define SDIO_MMC_PORT_AUTONTEN (0x01U << SDIO_MMC_PORT_AUTONTEN_Pos) ///< Automatic Ncr timer output enablement 192 #define SDIO_MMC_PORT_PDATS_Pos (5) 193 #define SDIO_MMC_PORT_PDATS (0x01U << SDIO_MMC_PORT_PDATS_Pos) ///< SD/MMC/SDIO port DAT line signal 194 #define SDIO_MMC_PORT_PCMDS_Pos (6) 195 #define SDIO_MMC_PORT_PCMDS (0x01U << SDIO_MMC_PORT_PCMDS_Pos) ///< SD/MMC/SDIO port CMD line signal 196 #define SDIO_MMC_PORT_PCLKS_Pos (7) 197 #define SDIO_MMC_PORT_PCLKS (0x01U << SDIO_MMC_PORT_PCLKS_Pos) ///< SD/MMC/SDIO port CLK line signal 198 //////////////////////////////////////////////////////////////////////////////// 199 /// @brief SDIO_MMC_INT_MASK Register Bit Definition 200 //////////////////////////////////////////////////////////////////////////////// 201 #define SDIO_MMC_INT_MASK_CMDDINT_Pos (0) 202 #define SDIO_MMC_INT_MASK_CMDDINT (0x01U << SDIO_MMC_INT_MASK_CMDDINT_Pos) ///<CMD completes interrupt shielding 203 #define SDIO_MMC_INT_MASK_DATDINT_Pos (1) 204 #define SDIO_MMC_INT_MASK_DATDINT (0x01U << SDIO_MMC_INT_MASK_DATDINT_Pos) ///< DAT completes interrupt shielding 205 #define SDIO_MMC_INT_MASK_DATEINT_Pos (2) 206 #define SDIO_MMC_INT_MASK_DATEINT (0x01U << SDIO_MMC_INT_MASK_DATEINT_Pos) ///< DAT CRC error interrupt masking 207 #define SDIO_MMC_INT_MASK_CMDEINT_Pos (3) 208 #define SDIO_MMC_INT_MASK_CMDEINT (0x01U << SDIO_MMC_INT_MASK_CMDEINT_Pos) ///< CMD CRC error interrupt masking 209 #define SDIO_MMC_INT_MASK_MBDINTM_Pos (4) 210 #define SDIO_MMC_INT_MASK_MBDINTM (0x01U << SDIO_MMC_INT_MASK_MBDINTM_Pos) ///< Multiple blocks complete interrupt shielding 211 #define SDIO_MMC_INT_MASK_MBTINTM_Pos (5) 212 #define SDIO_MMC_INT_MASK_MBTINTM (0x01U << SDIO_MMC_INT_MASK_MBTINTM_Pos) ///< Multiblock timeout interrupt shielding 213 #define SDIO_MMC_INT_MASK_CRTINTM_Pos (6) 214 #define SDIO_MMC_INT_MASK_CRTINTM (0x01U << SDIO_MMC_INT_MASK_CRTINTM_Pos) ///< Cmd and Resp Ncr timeout interrupt shielding 215 #define SDIO_MMC_INT_MASK_CRCINTM_Pos (7) 216 #define SDIO_MMC_INT_MASK_CRCINTM (0x01U << SDIO_MMC_INT_MASK_CRCINTM_Pos) ///< CRC status token error interrupt masking 217 #define SDIO_MMC_INT_MASK_D1INTM_Pos (8) 218 #define SDIO_MMC_INT_MASK_D1INTM (0x01U << SDIO_MMC_INT_MASK_D1INTM_Pos) ///< SDIO Data 1 Line Interrupt Mask 219 //////////////////////////////////////////////////////////////////////////////// 220 /// @brief SDIO_CLR_MMC_INT Register Bit Definition 221 //////////////////////////////////////////////////////////////////////////////// 222 #define SDIO_CLR_MMC_INT_CMDDMC_Pos (0) 223 #define SDIO_CLR_MMC_INT_CMDDMC (0x01U << SDIO_CLR_MMC_INT_CMDDMC_Pos) ///< CMD completes interrupt mask bit 224 #define SDIO_CLR_MMC_INT_DATDMC_Pos (1) 225 #define SDIO_CLR_MMC_INT_DATDMC (0x01U << SDIO_CLR_MMC_INT_DATDMC_Pos) ///< DAT completes interrupt mask bit 226 #define SDIO_CLR_MMC_INT_DATEMC_Pos (2) 227 #define SDIO_CLR_MMC_INT_DATEMC (0x01U << SDIO_CLR_MMC_INT_DATEMC_Pos) ///< DAT CRC error interrupt mask bit 228 #define SDIO_CLR_MMC_INT_CMDEMC_Pos (3) 229 #define SDIO_CLR_MMC_INT_CMDEMC (0x01U << SDIO_CLR_MMC_INT_CMDEMC_Pos) ///< CMD CRC error interrupt mask bit 230 #define SDIO_CLR_MMC_INT_MBDMC_Pos (4) 231 #define SDIO_CLR_MMC_INT_MBDMC (0x01U << SDIO_CLR_MMC_INT_MBDMC_Pos) ///< Multi - block transmission completion interrupt mask bit 232 #define SDIO_CLR_MMC_INT_MBTMC_Pos (5) 233 #define SDIO_CLR_MMC_INT_MBTMC (0x01U << SDIO_CLR_MMC_INT_MBTMC_Pos) ///< Multiblock transmission timeout interrupt mask bit 234 #define SDIO_CLR_MMC_INT_CRNTMC_Pos (6) 235 #define SDIO_CLR_MMC_INT_CRNTMC (0x01U << SDIO_CLR_MMC_INT_CRNTMC_Pos) ///< Command and response Ncr timeout interrupt mask bit 236 #define SDIO_CLR_MMC_INT_CRCEMC_Pos (7) 237 #define SDIO_CLR_MMC_INT_CRCEMC (0x01U << SDIO_CLR_MMC_INT_CRCEMC_Pos) ///< CRC status error marks the interrupt mask bit 238 #define SDIO_CLR_MMC_INT_D1MC_Pos (8) 239 #define SDIO_CLR_MMC_INT_D1MC (0x01U << SDIO_CLR_MMC_INT_D1MC_Pos) ///< SDIO DatA1 line interrupt flag/clear bit 240 #define SDIO_CLR_MMC_INT_MASK (0XFFU) 241 //////////////////////////////////////////////////////////////////////////////// 242 /// @brief SDIO_MMC_CARDSEL Register Bit Definition 243 //////////////////////////////////////////////////////////////////////////////// 244 #define SDIO_MMC_CARDSEL_TSCALE_Pos (0) 245 #define SDIO_MMC_CARDSEL_TSCALE (0x01U << SDIO_MMC_CARDSEL_TSCALE_Pos) ///< SD/MMC/SDIO clock frequency division factor (based on 1MHz 246 #define SDIO_MMC_CARDSEL_ENPCLK_Pos (6) 247 #define SDIO_MMC_CARDSEL_ENPCLK (0x01U << SDIO_MMC_CARDSEL_ENPCLK_Pos) ///< Enabling card's SD/MMC/SDIO port CLK clock 248 #define SDIO_MMC_CARDSEL_CTREN_Pos (7) 249 #define SDIO_MMC_CARDSEL_CTREN (0x01U << SDIO_MMC_CARDSEL_CTREN_Pos) ///< SD/MMC/SDIO controller enablement bit 250 #define SDIO_MMC_CARDSEL_MASK (0XFFU) 251 //////////////////////////////////////////////////////////////////////////////// 252 /// @brief SDIO_MMC_SIQ Register Bit Definition 253 //////////////////////////////////////////////////////////////////////////////// 254 #define SDIO_MMC_SIQ_PDAT0S_Pos (0) 255 #define SDIO_MMC_SIQ_PDAT0S (0x01U << SDIO_MMC_SIQ_PDAT0S_Pos) ///< SD/MMC/SDIO port DAT0 line signal 256 #define SDIO_MMC_SIQ_PDAT1S_Pos (1) 257 #define SDIO_MMC_SIQ_PDAT1S (0x01U << SDIO_MMC_SIQ_PDAT1S_Pos) ///< SD/MMC/SDIO port DAT1 line signal 258 #define SDIO_MMC_SIQ_PDAT2S_Pos (2) 259 #define SDIO_MMC_SIQ_PDAT2S (0x01U << SDIO_MMC_SIQ_PDAT2S_Pos) ///< SD/MMC/SDIO port DAT2 line signal 260 #define SDIO_MMC_SIQ_PDAT3S_Pos (3) 261 #define SDIO_MMC_SIQ_PDAT3S (0x01U << SDIO_MMC_SIQ_PDAT3S_Pos) ///< SD/MMC/SDIO port DAT3 line signal 262 #define SDIO_MMC_SIQ_CRC_status_Pos (4) 263 #define SDIO_MMC_SIQ_CRC_status (0x07U << SDIO_MMC_SIQ_CRC_status_Pos) ///< CRC state 264 #define SDIO_MMC_SIQ_PCMDS_Pos (7) 265 #define SDIO_MMC_SIQ_PCMDS (0x01U << SDIO_MMC_SIQ_PCMDS_Pos) ///< SD/MMC/SDIO port CMD line signal 266 //////////////////////////////////////////////////////////////////////////////// 267 /// @brief SDIO_MMC_IO_MBCTL Register Bit Definition 268 //////////////////////////////////////////////////////////////////////////////// 269 #define SDIO_MMC_IO_MBCTL_SPMBDTR_Pos (0) 270 #define SDIO_MMC_IO_MBCTL_SPMBDTR (0x01U << SDIO_MMC_IO_MBCTL_SPMBDTR_Pos) ///< Set the SD/MMC/SDIO port to automatically multiblock data transfer bit 271 #define SDIO_MMC_IO_MBCTL_SMBDTD_Pos (1) 272 #define SDIO_MMC_IO_MBCTL_SMBDTD (0x01U << SDIO_MMC_IO_MBCTL_SMBDTD_Pos) //< Multi - block data transfer direction selection bit 273 #define SDIO_MMC_IO_MBCTL_PAUTOTR_Pos (2) 274 #define SDIO_MMC_IO_MBCTL_PAUTOTR (0x01U << SDIO_MMC_IO_MBCTL_PAUTOTR_Pos) ///< Set up SD/MMC/SDIO port automatic command and multi - block data transfer 275 #define SDIO_MMC_IO_MBCTL_PCLKP_Pos (3) 276 #define SDIO_MMC_IO_MBCTL_PCLKP (0x01U << SDIO_MMC_IO_MBCTL_PCLKP_Pos) ///< SD/MMC/SDIO port CLK line polarity selection bit 277 #define SDIO_MMC_IO_MBCTL_BTSSel_Pos (4) 278 #define SDIO_MMC_IO_MBCTL_BTSSel (0x03U << SDIO_MMC_SIQ_CRC_status_Pos) ///< SD/MMC/SDIO BUSY Timeout level selects bits 279 #define SDIO_MMC_IO_MBCTL_BTSSel_2 (0x02U << SDIO_MMC_SIQ_CRC_status_Pos) ///< SD/MMC/SDIO BUSY Timeout level selects bits 280 #define SDIO_MMC_IO_MBCTL_NTSSel_Pos (6) 281 #define SDIO_MMC_IO_MBCTL_NTSSel (0x03U << SDIO_MMC_IO_MBCTL_NTSSel_Pos) ///< SD/MMC/SDIO NAC timeout level selection bit 282 //////////////////////////////////////////////////////////////////////////////// 283 /// @brief SDIO_MMC_BLOCKCNT Register Bit Definition 284 //////////////////////////////////////////////////////////////////////////////// 285 #define SDIO_MMC_BLOCKCNT_EN (0xFFFFU) ///< Block count register 286 //////////////////////////////////////////////////////////////////////////////// 287 /// @brief SDIO_MMC_TIMEOUTCNT Register Bit Definition 288 //////////////////////////////////////////////////////////////////////////////// 289 #define SDIO_MMC_TIMEOUTCNT_DTCNT (0xFFU) ///< Data transfer timeout count register 290 //////////////////////////////////////////////////////////////////////////////// 291 /// @brief SDIO_CMD_BUF0 Register Bit Definition 292 //////////////////////////////////////////////////////////////////////////////// 293 #define SDIO_CMD_BUF0_DAT (0xFFU) ///< Cmd_buf0 byte mapping bit 294 //////////////////////////////////////////////////////////////////////////////// 295 /// @brief SDIO_CMD_BUF1 Register Bit Definition 296 //////////////////////////////////////////////////////////////////////////////// 297 #define SDIO_CMD_BUF1_DAT (0xFFU) ///< Cmd_buf1 byte mapping bit 298 //////////////////////////////////////////////////////////////////////////////// 299 /// @brief SDIO_CMD_BUF2 Register Bit Definition 300 //////////////////////////////////////////////////////////////////////////////// 301 #define SDIO_CMD_BUF2_DAT (0xFFU) ///< Cmd_buf2 byte mapping bit 302 //////////////////////////////////////////////////////////////////////////////// 303 /// @brief SDIO_CMD_BUF3 Register Bit Definition 304 //////////////////////////////////////////////////////////////////////////////// 305 #define SDIO_CMD_BUF3_DAT (0xFFU) ///< Cmd_buf3 byte mapping bit 306 //////////////////////////////////////////////////////////////////////////////// 307 /// @brief SDIO_CMD_BUF4 Register Bit Definition 308 //////////////////////////////////////////////////////////////////////////////// 309 #define SDIO_CMD_BUF4_DAT (0xFFU) ///< Cmd_buf4 byte mapping bit 310 //////////////////////////////////////////////////////////////////////////////// 311 /// @brief SDIO_CMD_BUF5 Register Bit Definition 312 //////////////////////////////////////////////////////////////////////////////// 313 #define SDIO_CMD_BUF5_DAT (0xFFU) ///< Cmd_buf5 byte mapping bit 314 //////////////////////////////////////////////////////////////////////////////// 315 /// @brief SDIO_CMD_BUF6 Register Bit Definition 316 //////////////////////////////////////////////////////////////////////////////// 317 #define SDIO_CMD_BUF6_DAT (0xFFU) ///< Cmd_buf6 byte mapping bit 318 //////////////////////////////////////////////////////////////////////////////// 319 /// @brief SDIO_CMD_BUF7 Register Bit Definition 320 //////////////////////////////////////////////////////////////////////////////// 321 #define SDIO_CMD_BUF7_DAT (0xFFU) ///< Cmd_buf7 byte mapping bit 322 //////////////////////////////////////////////////////////////////////////////// 323 /// @brief SDIO_CMD_BUF8 Register Bit Definition 324 //////////////////////////////////////////////////////////////////////////////// 325 #define SDIO_CMD_BUF8_DAT (0xFFU) ///< Cmd_buf8 byte mapping bit 326 //////////////////////////////////////////////////////////////////////////////// 327 /// @brief SDIO_CMD_BUF9 Register Bit Definition 328 //////////////////////////////////////////////////////////////////////////////// 329 #define SDIO_CMD_BUF9_DAT (0xFFU) ///< Cmd_buf9 byte mapping bit 330 //////////////////////////////////////////////////////////////////////////////// 331 /// @brief SDIO_CMD_BUF10 Register Bit Definition 332 //////////////////////////////////////////////////////////////////////////////// 333 #define SDIO_CMD_BUF10_DAT (0xFFU) ///< Cmd_buf10 byte mapping bit 334 //////////////////////////////////////////////////////////////////////////////// 335 /// @brief SDIO_CMD_BUF11 Register Bit Definition 336 //////////////////////////////////////////////////////////////////////////////// 337 #define SDIO_CMD_BUF11_DAT (0xFFU) ///< Cmd_buf11 byte mapping bit 338 //////////////////////////////////////////////////////////////////////////////// 339 /// @brief SDIO_CMD_BUF12 Register Bit Definition 340 //////////////////////////////////////////////////////////////////////////////// 341 #define SDIO_CMD_BUF12_DAT (0xFFU) ///< Cmd_buf12 byte mapping bit 342 //////////////////////////////////////////////////////////////////////////////// 343 /// @brief SDIO_CMD_BUF13 Register Bit Definition 344 //////////////////////////////////////////////////////////////////////////////// 345 #define SDIO_CMD_BUF13_DAT (0xFFU) ///< Cmd_buf13 byte mapping bit 346 //////////////////////////////////////////////////////////////////////////////// 347 /// @brief SDIO_CMD_BUF14 Register Bit Definition 348 //////////////////////////////////////////////////////////////////////////////// 349 #define SDIO_CMD_BUF14_DAT (0xFFU) ///< Cmd_buf14 byte mapping bit 350 //////////////////////////////////////////////////////////////////////////////// 351 /// @brief SDIO_CMD_BUF15 Register Bit Definition 352 //////////////////////////////////////////////////////////////////////////////// 353 #define SDIO_CMD_BUF15_DAT (0xFFU) ///< Cmd_buf15 byte mapping bit 354 //////////////////////////////////////////////////////////////////////////////// 355 /// @brief SDIO_BUF_CTLL Register Bit Definition 356 //////////////////////////////////////////////////////////////////////////////// 357 #define SDIO_BUF_CTLL_DBF_Pos (0) 358 #define SDIO_BUF_CTLL_DBF (0x01U << SDIO_BUF_CTLL_DBF_Pos) ///< The data cache is full 359 #define SDIO_BUF_CTLL_DBE_Pos (1) 360 #define SDIO_BUF_CTLL_DBE (0x01U << SDIO_BUF_CTLL_DBE_Pos) ///< Data buff is null 361 #define SDIO_BUF_CTLL_DBML_Pos (2) 362 #define SDIO_BUF_CTLL_DBML (0xFFU << SDIO_BUF_CTLL_DBML_Pos) ////< Data buff tags 363 #define SDIO_BUF_CTLL_DMAHEN_Pos (10) 364 #define SDIO_BUF_CTLL_DMAHEN (0x01U << SDIO_BUF_CTLL_DMAHEN_Pos) ///< DMA hardware interface enablement 365 #define SDIO_BUF_CTLL_SBAD_Pos (11) 366 #define SDIO_BUF_CTLL_SBAD (0x01U << SDIO_BUF_CTLL_SBAD_Pos) ///< Sets the access direction of the buff 367 #define SDIO_BUF_CTLL_DFIFOSM_Pos (12) 368 #define SDIO_BUF_CTLL_DFIFOSM (0x01U << SDIO_BUF_CTLL_DFIFOSM_Pos) ///< Data FIFO status signal shielding bit 369 #define SDIO_BUF_CTLL_DRM_Pos (14) 370 #define SDIO_BUF_CTLL_DRM (0x01U << SDIO_BUF_CTLL_DRM_Pos) ///< DMA request masking 371 #define SDIO_BUF_CTLL_DBFEN_Pos (15) 372 #define SDIO_BUF_CTLL_DBFEN (0x01U << SDIO_BUF_CTLL_DBFEN_Pos) ///< Data Buf empty enable bit 373 //////////////////////////////////////////////////////////////////////////////// 374 /// @brief SDIO_DATA_BUF Register Bit Definition 375 //////////////////////////////////////////////////////////////////////////////// 376 #define SDIO_DATA_BUF_DB (0xFFFFFFFFU) ///< Data buffer 377 378 379 380 381 382 383 /// @} 384 385 /// @} 386 387 /// @} 388 389 //////////////////////////////////////////////////////////////////////////////// 390 #endif 391 //////////////////////////////////////////////////////////////////////////////// 392