1 //////////////////////////////////////////////////////////////////////////////// 2 /// @file reg_wwdg.h 3 /// @author AE TEAM 4 /// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF 5 /// MM32 FIRMWARE LIBRARY. 6 //////////////////////////////////////////////////////////////////////////////// 7 /// @attention 8 /// 9 /// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE 10 /// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE 11 /// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR 12 /// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH 13 /// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN 14 /// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS. 15 /// 16 /// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2> 17 //////////////////////////////////////////////////////////////////////////////// 18 19 // Define to prevent recursive inclusion 20 21 #ifndef __REG_WWDG_H 22 #define __REG_WWDG_H 23 24 // Files includes 25 26 #include <stdint.h> 27 #include <stdbool.h> 28 #include "types.h" 29 30 31 32 33 #if defined ( __CC_ARM ) 34 #pragma anon_unions 35 #endif 36 37 38 39 40 41 42 43 44 45 46 47 //////////////////////////////////////////////////////////////////////////////// 48 /// @brief WWDG Base Address Definition 49 //////////////////////////////////////////////////////////////////////////////// 50 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) ///< Base Address: 0x40002C00 51 52 53 54 //////////////////////////////////////////////////////////////////////////////// 55 /// @brief WWDG Register Structure Definition 56 //////////////////////////////////////////////////////////////////////////////// 57 #undef USENCOMBINEREGISTER 58 #undef USENNEWREGISTER 59 #undef USENOLDREGISTER 60 #define USENCOMBINEREGISTER 61 #ifdef USENCOMBINEREGISTER 62 typedef struct { 63 __IO u32 CR; ///< Control register offset: 0x00 64 union { 65 __IO u32 CFGR; ///< Configuration register offset: 0x04 66 __IO u32 CFR; 67 }; 68 __IO u32 SR; ///< Status register offset: 0x08 69 } WWDG_TypeDef; 70 #endif 71 #ifdef USENNEWREGISTER 72 typedef struct { 73 __IO u32 CR; ///< Control register offset: 0x00 74 __IO u32 CFGR; ///< Configuration register offset: 0x04 75 __IO u32 SR; ///< Status register offset: 0x08 76 } WWDG_TypeDef; 77 #endif 78 #ifdef USENOLDREGISTER 79 typedef struct { 80 __IO u32 CR; 81 __IO u32 CFR; 82 __IO u32 SR; 83 } WWDG_TypeDef; 84 #endif 85 86 87 //////////////////////////////////////////////////////////////////////////////// 88 /// @brief WWDG type pointer Definition 89 //////////////////////////////////////////////////////////////////////////////// 90 #define WWDG ((WWDG_TypeDef*) WWDG_BASE) 91 92 93 94 //////////////////////////////////////////////////////////////////////////////// 95 /// @brief WWDG_CR Register Bit Definition 96 //////////////////////////////////////////////////////////////////////////////// 97 #define WWDG_CR_CNT_Pos (0) 98 #define WWDG_CR_CNT (0x7FU << WWDG_CR_CNT_Pos) ///< T[6:0] bits (7-Bit counter (MSB to LSB)) 99 #define WWDG_CR_WDGA_Pos (7) 100 #define WWDG_CR_WDGA (0x01U << WWDG_CR_WDGA_Pos) ///< Activation bit 101 102 //////////////////////////////////////////////////////////////////////////////// 103 /// @brief WWDG_CFR Register Bit Definition 104 //////////////////////////////////////////////////////////////////////////////// 105 #define WWDG_CFGR_WINDOW_Pos (0) 106 #define WWDG_CFGR_WINDOW (0x7FU << WWDG_CFGR_WINDOW_Pos) ///< W[6:0] bits (7-bit window value) 107 #define WWDG_CFGR_WDGTB_Pos (7) 108 #define WWDG_CFGR_WDGTB (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base) 109 #define WWDG_CFGR_WDGTB_1 (0x00U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /1) 110 #define WWDG_CFGR_WDGTB_2 (0x01U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /2) 111 #define WWDG_CFGR_WDGTB_4 (0x02U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /4) 112 #define WWDG_CFGR_WDGTB_8 (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /8) 113 #define WWDG_CFGR_EWI_Pos (9) 114 #define WWDG_CFGR_EWI (0x01U << WWDG_CFGR_EWI_Pos) ///< Early Wakeup Interrupt 115 116 //////////////////////////////////////////////////////////////////////////////// 117 /// @brief WWDG_SR Register Bit Definition 118 //////////////////////////////////////////////////////////////////////////////// 119 #define WWDG_SR_EWIF_Pos (0) 120 #define WWDG_SR_EWIF (0x01U << WWDG_SR_EWIF_Pos) ///< Early Wakeup Interrupt Flag 121 122 123 124 125 /// @} 126 127 /// @} 128 129 /// @} 130 131 //////////////////////////////////////////////////////////////////////////////// 132 #endif 133 //////////////////////////////////////////////////////////////////////////////// 134