1; *************************************************************
2; *** Scatter-Loading Description File generated by uVision ***
3; *************************************************************
4
5#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m33 -xc
6; command above MUST be in first line (no comment above!)
7
8/*
9;-------- <<< Use Configuration Wizard in Context Menu >>> -------------------
10*/
11
12/*--------------------- Flash Configuration ----------------------------------
13; <h> Flash Configuration
14;   <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
15;   <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
16; </h>
17 *----------------------------------------------------------------------------*/
18#define __ROM_BASE     0x008000000
19#define __ROM_SIZE     0x000040000
20
21/*---------------------------- ITCM Configuration -----------------------------
22; <h> ITCM Configuration
23;   <o0> ITCM Base Address    <0x0-0xFFFFFFFF:8>
24;   <o1> ITCM Size (in Bytes) <0x0-0xFFFFFFFF:8>
25; </h>
26 *----------------------------------------------------------------------------*/
27#define __ITCM_BASE     0x00000000
28#define __ITCM_SIZE     0x00008000
29
30/*---------------------------- DTCM Configuration -----------------------------
31; <h> DTCM Configuration
32;   <o0> DTCM Base Address    <0x0-0xFFFFFFFF:8>
33;   <o1> DTCM Size (in Bytes) <0x0-0xFFFFFFFF:8>
34; </h>
35 *----------------------------------------------------------------------------*/
36#define __DTCM_BASE     0x20000000
37#define __DTCM_SIZE     0x00008000
38
39/*--------------------- Embedded RAM1 Configuration ---------------------------
40; <h> RAM Configuration
41;   <o0> RAM1 Base Address    <0x0-0xFFFFFFFF:8>
42;   <o1> RAM1 Size (in Bytes) <0x0-0xFFFFFFFF:8>
43; </h>
44 *----------------------------------------------------------------------------*/
45#define __RAM1_BASE     0x30000000
46#define __RAM1_SIZE     0x0001C000
47
48/*--------------------- Embedded RAM2 Configuration ---------------------------
49; <h> RAM Configuration
50;   <o0> RAM2 Base Address    <0x0-0xFFFFFFFF:8>
51;   <o1> RAM2 Size (in Bytes) <0x0-0xFFFFFFFF:8>
52; </h>
53 *----------------------------------------------------------------------------*/
54#define __RAM2_BASE     0x3001C000
55#define __RAM2_SIZE     0x00004000
56
57
58/*--------------------- Stack / Heap Configuration ---------------------------
59; <h> Stack / Heap Configuration
60;   <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
61;   <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
62; </h>
63 *----------------------------------------------------------------------------*/
64#define __STACK_SIZE       0x00000800
65#define __HEAP_SIZE        0x00000C00
66
67
68/*----------------------------------------------------------------------------
69  User Stack & Heap boundary definition
70 *----------------------------------------------------------------------------*/
71#define __STACK_TOP        (__RAM1_BASE + __RAM1_SIZE)    /* starts at end of RAM */
72#define __HEAP_BASE        (AlignExpr(+0, 8))             /* starts after RW_RAM section, 8 byte aligned */
73
74
75/*----------------------------------------------------------------------------
76  Scatter File Definitions definition
77 *----------------------------------------------------------------------------*/
78#define __RO_BASE         __ROM_BASE
79#define __RO_SIZE         __ROM_SIZE
80
81LR_ROM __RO_BASE __RO_SIZE  {                       ; load region size_region
82  ER_ROM __RO_BASE __RO_SIZE  {                     ; load address = execution address
83   *.o (RESET, +First)
84   *(InRoot$$Sections)
85;   *(Veneer$$CMSE)                                 ; uncomment for secure applications
86   .ANY (+RO)
87   .ANY (+XO)
88  }
89
90  RW_ITCM __ITCM_BASE __ITCM_SIZE  {                ; RW data
91   .ANY (+RW +ZI)
92  }
93
94  RW_DTCM __DTCM_BASE __DTCM_SIZE  {                ; RW data
95   .ANY (+RW +ZI)
96  }
97
98  RW_RAM1 __RAM1_BASE (__RAM1_SIZE - __STACK_SIZE - __HEAP_SIZE)  {                     ; RW data
99   .ANY (+RW +ZI)
100  }
101
102  RW_RAM2 __RAM2_BASE __RAM2_SIZE  {                ; RW data
103   .ANY (+RW +ZI)
104  }
105
106#if __HEAP_SIZE > 0
107  ARM_LIB_HEAP  __HEAP_BASE EMPTY  __HEAP_SIZE  {   ; Reserve empty region for heap
108  }
109#endif
110
111  ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE {   ; Reserve empty region for stack
112  }
113}
114
115