1 /** 2 ****************************************************************************** 3 * @file HAL_rcc.h 4 * @author AE Team 5 * @version V2.0.0 6 * @date 22/08/2017 7 * @brief This file contains all the functions prototypes for the RCC firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2017 MindMotion</center></h2> 20 */ 21 //SJH&TM change 22 23 /* Define to prevent recursive inclusion -------------------------------------*/ 24 #ifndef __HAL_RCC_H 25 #define __HAL_RCC_H 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "HAL_device.h" 29 30 /** @addtogroup StdPeriph_Driver 31 * @{ 32 */ 33 34 /** @addtogroup RCC 35 * @{ 36 */ 37 38 /** @defgroup RCC_Exported_Types 39 * @{ 40 */ 41 42 typedef struct 43 { 44 uint32_t SYSCLK_Frequency; 45 uint32_t HCLK_Frequency; 46 uint32_t PCLK1_Frequency; 47 uint32_t PCLK2_Frequency; 48 }RCC_ClocksTypeDef; 49 50 /** 51 * @} 52 */ 53 54 /** @defgroup RCC_Exported_Constants 55 * @{ 56 */ 57 58 /** @defgroup HSE_configuration 59 * @{ 60 */ 61 62 #define RCC_HSE_OFF ((uint32_t)0x00000000) 63 #define RCC_HSE_ON ((uint32_t)0x00010000) 64 #define RCC_HSE_Bypass ((uint32_t)0x00040000) 65 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 66 ((HSE) == RCC_HSE_Bypass)) 67 68 /** 69 * @} 70 */ 71 72 /** @defgroup PLL_entry_clock_source 73 * @{ 74 */ 75 76 #define RCC_PLLSource_HSI_Div4 ((uint32_t)0x00000000) 77 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) 78 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) 79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ 80 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 81 ((SOURCE) == RCC_PLLSource_HSE_Div2)) 82 /** 83 * @} 84 */ 85 86 87 /** @defgroup System_clock_source 88 * @{ 89 */ 90 91 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 92 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 93 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 94 #define RCC_SYSCLKSource_LSI ((uint32_t)0x00000003) 95 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 96 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 97 ((SOURCE) == RCC_SYSCLKSource_PLLCLK||(SOURCE) == RCC_SYSCLKSource_LSI)) 98 /** 99 * @} 100 */ 101 102 /** @defgroup AHB_clock_source 103 * @{ 104 */ 105 106 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 107 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 108 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 109 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 110 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 111 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 112 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 113 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 114 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 115 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 116 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 117 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 118 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 119 ((HCLK) == RCC_SYSCLK_Div512)) 120 /** 121 * @} 122 */ 123 124 /** @defgroup APB1_APB2_clock_source 125 * @{ 126 */ 127 128 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 129 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 130 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 131 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 132 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 133 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 134 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 135 ((PCLK) == RCC_HCLK_Div16)) 136 137 /** 138 * @} 139 */ 140 141 /** @defgroup PLL_multiplication_factor 142 * @{ 143 */ 144 145 #define RCC_PLLMul_2 ((uint32_t)0x00000000) 146 #define RCC_PLLMul_3 ((uint32_t)0x00040000) 147 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 148 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 149 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 150 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 151 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 152 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 153 #define RCC_PLLMul_10 ((uint32_t)0x00200000) 154 #define RCC_PLLMul_11 ((uint32_t)0x00240000) 155 #define RCC_PLLMul_12 ((uint32_t)0x00280000) 156 #define RCC_PLLMul_13 ((uint32_t)0x002C0000) 157 #define RCC_PLLMul_14 ((uint32_t)0x00300000) 158 #define RCC_PLLMul_15 ((uint32_t)0x00340000) 159 #define RCC_PLLMul_16 ((uint32_t)0x00380000) 160 161 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 162 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 163 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 164 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 165 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 166 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 167 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 168 ((MUL) == RCC_PLLMul_16)) 169 170 171 /** 172 * @} 173 */ 174 175 /** @defgroup RCC_Interrupt_source 176 * @{ 177 */ 178 179 #define RCC_IT_LSIRDY ((uint8_t)0x01) 180 #define RCC_IT_HSIRDY ((uint8_t)0x04) 181 #define RCC_IT_HSERDY ((uint8_t)0x08) 182 #define RCC_IT_PLLRDY ((uint8_t)0x10) 183 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 184 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || \ 185 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 186 ((IT) == RCC_IT_PLLRDY)) 187 188 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 189 /** 190 * @} 191 */ 192 193 /** @defgroup USB_clock_source 194 * @{ 195 */ 196 197 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint32_t)0x00000000) 198 #define RCC_USBCLKSource_PLLCLK_Div2 ((uint32_t)0x00400000) 199 #define RCC_USBCLKSource_PLLCLK_Div3 ((uint32_t)0x00800000) 200 #define RCC_USBCLKSource_PLLCLK_Div4 ((uint32_t)0x00c00000) 201 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \ 202 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2) || ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div3)|| \ 203 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div4)) 204 205 206 /** @defgroup AHB_peripheral 207 * @{ 208 */ 209 210 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) 211 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 212 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) 213 #define RCC_AHBPeriph_AES ((uint32_t)0x00000080) 214 #define RCC_AHBPeriph_GPIOA ((uint32_t)0x00020000) 215 #define RCC_AHBPeriph_GPIOB ((uint32_t)0x00040000) 216 #define RCC_AHBPeriph_GPIOC ((uint32_t)0x00080000) 217 #define RCC_AHBPeriph_GPIOD ((uint32_t)0x00100000) 218 219 220 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFE1FF6A) == 0x00) && ((PERIPH) != 0x00)) 221 /** 222 * @} 223 */ 224 225 /** @defgroup APB2_peripheral 226 * @{ 227 */ 228 229 #define RCC_APB2Periph_SYSCFG ((uint32_t)0x00000001) 230 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) 231 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) 232 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 233 #define RCC_APB2Periph_UART1 ((uint32_t)0x00004000) 234 #define RCC_APB2Periph_COMP ((uint32_t)0x00008000) 235 #define RCC_APB2Periph_TIM14 ((uint32_t)0x00010000) 236 #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) 237 #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) 238 #define RCC_APB2Periph_DBGMCU ((uint32_t)0x00400000) 239 #define RCC_APB2Periph_ALL ((uint32_t)0x0047DA01) 240 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB825FE) == 0x00) && ((PERIPH) != 0x00)) 241 /** 242 * @} 243 */ 244 245 /** @defgroup APB1_peripheral 246 * @{ 247 */ 248 249 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 250 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 251 252 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 253 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 254 #define RCC_APB1Periph_UART2 ((uint32_t)0x00020000) 255 256 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 257 258 #define RCC_APB1Periph_USB ((uint32_t)0x00800000) 259 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 260 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 261 #define RCC_APB1Periph_CRS ((uint32_t)0x08000000) 262 263 #define RCC_APB1Periph_ALL ((uint32_t)0x1AA24803) 264 265 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xE55DB7FC) == 0x00) && ((PERIPH) != 0x00)) 266 /** 267 * @} 268 */ 269 270 /** @defgroup Clock_source_to_output_on_MCO_pin 271 * @{ 272 */ 273 274 #define RCC_MCO_NoClock ((uint8_t)0x00) 275 #define RCC_MCO_SYSCLK ((uint8_t)0x04) 276 #define RCC_MCO_HSI ((uint8_t)0x05) 277 #define RCC_MCO_HSE ((uint8_t)0x06) 278 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) 279 #define RCC_MCO_LSI ((uint8_t)0x02) 280 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 281 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 282 ((MCO) == RCC_MCO_PLLCLK_Div2)||((MCO) == RCC_MCO_LSI)) 283 /** 284 * @} 285 */ 286 287 /** @defgroup RCC_Flag 288 * @{ 289 */ 290 291 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 292 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 293 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 294 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 295 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 296 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 297 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 298 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 299 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 300 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 301 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 302 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 303 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 304 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)) 305 306 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 307 /** 308 * @} 309 */ 310 311 /** 312 * @} 313 */ 314 315 /** @defgroup RCC_Exported_Macros 316 * @{ 317 */ 318 319 /** 320 * @} 321 */ 322 323 /** @defgroup RCC_Exported_Functions 324 * @{ 325 */ 326 327 void RCC_DeInit(void); 328 void RCC_HSEConfig(uint32_t RCC_HSE); 329 ErrorStatus RCC_WaitForHSEStartUp(void); 330 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 331 void RCC_HSICmd(FunctionalState NewState); 332 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 333 void RCC_PLLCmd(FunctionalState NewState); 334 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 335 uint8_t RCC_GetSYSCLKSource(void); 336 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 337 void RCC_PCLK1Config(uint32_t RCC_HCLK); 338 void RCC_PCLK2Config(uint32_t RCC_HCLK); 339 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 340 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); 341 void RCC_LSICmd(FunctionalState NewState); 342 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 343 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 344 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 345 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 346 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 347 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 348 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 349 void RCC_MCOConfig(uint8_t RCC_MCO); 350 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 351 void RCC_ClearFlag(void); 352 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 353 void RCC_ClearITPendingBit(uint8_t RCC_IT); 354 355 #endif /* __HAL_RCC_H */ 356 /** 357 * @} 358 */ 359 360 /** 361 * @} 362 */ 363 364 /** 365 * @} 366 */ 367 368 /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/ 369