1 /**
2 ******************************************************************************
3 * @file  HAL_dma.c
4 * @author  AE Team
5 * @version  V2.0.0
6 * @date  22/08/2017
7 * @brief  This file provides all the DMA firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>&copy; COPYRIGHT 2017 MindMotion</center></h2>
19 */
20 
21 /* Includes ------------------------------------------------------------------*/
22 #include "HAL_dma.h"
23 
24 
25 /** @addtogroup StdPeriph_Driver
26 * @{
27 */
28 
29 /** @defgroup DMA
30 * @brief DMA driver modules
31 * @{
32 */
33 
34 /** @defgroup DMA_Private_TypesDefinitions
35 * @{
36 */
37 /**
38 * @}
39 */
40 
41 /** @defgroup DMA_Private_Defines
42 * @{
43 */
44 
45 /* DMA ENABLE mask */
46 #define CCR_ENABLE_Set          ((uint32_t)0x00000001)
47 #define CCR_ENABLE_Reset        ((uint32_t)0xFFFFFFFE)
48 
49 /* DMA1 Channelx interrupt pending bit masks */
50 #define DMA1_Channel1_IT_Mask    ((uint32_t)0x0000000F)
51 #define DMA1_Channel2_IT_Mask    ((uint32_t)0x000000F0)
52 #define DMA1_Channel3_IT_Mask    ((uint32_t)0x00000F00)
53 #define DMA1_Channel4_IT_Mask    ((uint32_t)0x0000F000)
54 #define DMA1_Channel5_IT_Mask    ((uint32_t)0x000F0000)
55 
56 
57 
58 
59 
60 /* DMA registers Masks */
61 #define CCR_CLEAR_Mask           ((uint32_t)0xFFFF800F)
62 
63 /**
64 * @}
65 */
66 
67 /** @defgroup DMA_Private_Macros
68 * @{
69 */
70 
71 /**
72 * @}
73 */
74 
75 /** @defgroup DMA_Private_Variables
76 * @{
77 */
78 
79 /**
80 * @}
81 */
82 
83 /** @defgroup DMA_Private_FunctionPrototypes
84 * @{
85 */
86 
87 /**
88 * @}
89 */
90 
91 /** @defgroup DMA_Private_Functions
92 * @{
93 */
94 
95 /**
96 * @brief  Deinitializes the DMAy Channelx registers to their default reset
97 *   values.
98 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
99 *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
100 *   DMA Channel.
101 * @retval : None
102 */
DMA_DeInit(DMA_Channel_TypeDef * DMAy_Channelx)103 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
104 {
105     /* Check the parameters */
106     assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
107     /* Disable the selected DMAy Channelx */
108     DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
109     /* Reset DMAy Channelx control register */
110     DMAy_Channelx->CCR  = 0;
111 
112     /* Reset DMAy Channelx remaining bytes register */
113     DMAy_Channelx->CNDTR = 0;
114 
115     /* Reset DMAy Channelx peripheral address register */
116     DMAy_Channelx->CPAR  = 0;
117 
118     /* Reset DMAy Channelx memory address register */
119     DMAy_Channelx->CMAR = 0;
120     switch (*(uint32_t*)&DMAy_Channelx)
121     {
122     case DMA1_Channel1_BASE:
123         /* Reset interrupt pending bits for DMA1 Channel1 */
124         DMA1->IFCR |= DMA1_Channel1_IT_Mask;
125         break;
126     case DMA1_Channel2_BASE:
127         /* Reset interrupt pending bits for DMA1 Channel2 */
128         DMA1->IFCR |= DMA1_Channel2_IT_Mask;
129         break;
130     case DMA1_Channel3_BASE:
131         /* Reset interrupt pending bits for DMA1 Channel3 */
132         DMA1->IFCR |= DMA1_Channel3_IT_Mask;
133         break;
134     case DMA1_Channel4_BASE:
135         /* Reset interrupt pending bits for DMA1 Channel4 */
136         DMA1->IFCR |= DMA1_Channel4_IT_Mask;
137         break;
138     case DMA1_Channel5_BASE:
139         /* Reset interrupt pending bits for DMA1 Channel5 */
140         DMA1->IFCR |= DMA1_Channel5_IT_Mask;
141         break;
142 
143 
144     default:
145         break;
146     }
147 }
148 
149 /**
150 * @brief  Initializes the DMAy Channelx according to the specified
151 *   parameters in the DMA_InitStruct.
152 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
153 *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
154 *   DMA Channel.
155 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
156 *   contains the configuration information for the specified
157 *   DMA Channel.
158 * @retval : None
159 */
DMA_Init(DMA_Channel_TypeDef * DMAy_Channelx,DMA_InitTypeDef * DMA_InitStruct)160 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
161 {
162     uint32_t tmpreg = 0;
163     /* Check the parameters */
164     assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
165     assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
166     assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
167     assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
168     assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
169     assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
170     assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
171     assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
172     assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
173     assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
174     /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
175     /* Get the DMAy_Channelx CCR value */
176     tmpreg = DMAy_Channelx->CCR;
177     /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
178     tmpreg &= CCR_CLEAR_Mask;
179     /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
180     /* Set DIR bit according to DMA_DIR value */
181     /* Set CIRC bit according to DMA_Mode value */
182     /* Set PINC bit according to DMA_PeripheralInc value */
183     /* Set MINC bit according to DMA_MemoryInc value */
184     /* Set PSIZE bits according to DMA_PeripheralDataSize value */
185     /* Set MSIZE bits according to DMA_MemoryDataSize value */
186     /* Set PL bits according to DMA_Priority value */
187     /* Set the MEM2MEM bit according to DMA_M2M value */
188     tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
189         DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
190             DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
191                 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
192     /* Write to DMAy Channelx CCR */
193     DMAy_Channelx->CCR = tmpreg;
194     /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
195     /* Write to DMAy Channelx CNDTR */
196     DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
197     /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
198     /* Write to DMAy Channelx CPAR */
199     DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
200     /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
201     /* Write to DMAy Channelx CMAR */
202     DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
203 }
204 
205 /**
206 * @brief  Fills each DMA_InitStruct member with its default value.
207 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure
208 *   which will be initialized.
209 * @retval : None
210 */
DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct)211 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
212 {
213     /*-------------- Reset DMA init structure parameters values ------------------*/
214     /* Initialize the DMA_PeripheralBaseAddr member */
215     DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
216     /* Initialize the DMA_MemoryBaseAddr member */
217     DMA_InitStruct->DMA_MemoryBaseAddr = 0;
218     /* Initialize the DMA_DIR member */
219     DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
220     /* Initialize the DMA_BufferSize member */
221     DMA_InitStruct->DMA_BufferSize = 0;
222     /* Initialize the DMA_PeripheralInc member */
223     DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
224     /* Initialize the DMA_MemoryInc member */
225     DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
226     /* Initialize the DMA_PeripheralDataSize member */
227     DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
228     /* Initialize the DMA_MemoryDataSize member */
229     DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
230     /* Initialize the DMA_Mode member */
231     DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
232     /* Initialize the DMA_Priority member */
233     DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
234     /* Initialize the DMA_M2M member */
235     DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
236 }
237 
238 /**
239 * @brief  Enables or disables the specified DMAy Channelx.
240 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
241 *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
242 *   DMA Channel.
243 * @param NewState: new state of the DMAy Channelx.
244 *   This parameter can be: ENABLE or DISABLE.
245 * @retval : None
246 */
DMA_Cmd(DMA_Channel_TypeDef * DMAy_Channelx,FunctionalState NewState)247 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
248 {
249     /* Check the parameters */
250     assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
251     assert_param(IS_FUNCTIONAL_STATE(NewState));
252     if (NewState != DISABLE)
253     {
254         /* Enable the selected DMAy Channelx */
255         DMAy_Channelx->CCR |= CCR_ENABLE_Set;
256     }
257     else
258     {
259         /* Disable the selected DMAy Channelx */
260         DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
261     }
262 }
263 
264 /**
265 * @brief  Enables or disables the specified DMAy Channelx interrupts.
266 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
267 *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
268 *   DMA Channel.
269 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
270 *   or disabled.
271 *   This parameter can be any combination of the following values:
272 * @arg DMA_IT_TC:  Transfer complete interrupt mask
273 * @arg DMA_IT_HT:  Half transfer interrupt mask
274 * @arg DMA_IT_TE:  Transfer error interrupt mask
275 * @param NewState: new state of the specified DMA interrupts.
276 *   This parameter can be: ENABLE or DISABLE.
277 * @retval : None
278 */
DMA_ITConfig(DMA_Channel_TypeDef * DMAy_Channelx,uint32_t DMA_IT,FunctionalState NewState)279 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
280 {
281     /* Check the parameters */
282     assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
283     assert_param(IS_DMA_CONFIG_IT(DMA_IT));
284     assert_param(IS_FUNCTIONAL_STATE(NewState));
285     if (NewState != DISABLE)
286     {
287         /* Enable the selected DMA interrupts */
288         DMAy_Channelx->CCR |= DMA_IT;
289     }
290     else
291     {
292         /* Disable the selected DMA interrupts */
293         DMAy_Channelx->CCR &= ~DMA_IT;
294     }
295 }
296 
297 /**
298 * @brief  Returns the number of remaining data units in the current
299 *   DMAy Channelx transfer.
300 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
301 *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
302 *   DMA Channel.
303 * @retval : The number of remaining data units in the current DMAy Channelx
304 *   transfer.
305 */
DMA_GetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx)306 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
307 {
308     /* Check the parameters */
309     assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
310     /* Return the number of remaining data units for DMAy Channelx */
311     return ((uint16_t)(DMAy_Channelx->CNDTR));
312 }
313 
314 /**
315 * @brief  Checks whether the specified DMAy Channelx flag is set or not.
316 * @param DMA_FLAG: specifies the flag to check.
317 *   This parameter can be one of the following values:
318 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
319 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
320 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
321 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
322 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
323 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
324 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
325 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
326 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
327 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
328 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
329 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
330 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
331 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
332 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
333 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
334 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
335 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
336 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
337 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
338 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
339 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
340 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
341 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
342 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
343 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
344 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
345 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
346 * @retval : The new state of DMA_FLAG (SET or RESET).
347 */
DMA_GetFlagStatus(uint32_t DMA_FLAG)348 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
349 {
350     FlagStatus bitstatus = RESET;
351     uint32_t tmpreg = 0;
352     /* Check the parameters */
353     assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
354 
355     /* Get DMA1 ISR register value */
356     tmpreg = DMA1->ISR ;
357 
358     /* Check the status of the specified DMA flag */
359     if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
360     {
361         /* DMA_FLAG is set */
362         bitstatus = SET;
363     }
364     else
365     {
366         /* DMA_FLAG is reset */
367         bitstatus = RESET;
368     }
369 
370     /* Return the DMA_FLAG status */
371     return  bitstatus;
372 }
373 
374 /**
375 * @brief  Clears the DMAy Channelx's pending flags.
376 * @param DMA_FLAG: specifies the flag to clear.
377 *   This parameter can be any combination (for the same DMA) of
378 *   the following values:
379 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
380 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
381 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
382 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
383 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
384 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
385 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
386 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
387 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
388 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
389 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
390 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
391 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
392 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
393 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
394 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
395 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
396 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
397 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
398 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
399 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
400 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
401 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
402 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
403 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
404 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
405 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
406 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
407 * @retval : None
408 */
DMA_ClearFlag(uint32_t DMA_FLAG)409 void DMA_ClearFlag(uint32_t DMA_FLAG)
410 {
411     /* Check the parameters */
412     assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
413 
414     /* Clear the selected DMA flags */
415     DMA1->IFCR = DMA_FLAG;
416 }
417 
418 /**
419 * @brief  Checks whether the specified DMAy Channelx interrupt has
420 *   occurred or not.
421 * @param DMA_IT: specifies the DMA interrupt source to check.
422 *   This parameter can be one of the following values:
423 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
424 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
425 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
426 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
427 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
428 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
429 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
430 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
431 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
432 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
433 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
434 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
435 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
436 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
437 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
438 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
439 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
440 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
441 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
442 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
443 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
444 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
445 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
446 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
447 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
448 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
449 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
450 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
451 * @retval : The new state of DMA_IT (SET or RESET).
452 */
DMA_GetITStatus(uint32_t DMA_IT)453 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
454 {
455     ITStatus bitstatus = RESET;
456     uint32_t tmpreg = 0;
457     /* Check the parameters */
458     assert_param(IS_DMA_GET_IT(DMA_IT));
459 
460     /* Get DMA1 ISR register value */
461     tmpreg = DMA1->ISR ;
462 
463     /* Check the status of the specified DMA interrupt */
464     if ((tmpreg & DMA_IT) != (uint32_t)RESET)
465     {
466         /* DMA_IT is set */
467         bitstatus = SET;
468     }
469     else
470     {
471         /* DMA_IT is reset */
472         bitstatus = RESET;
473     }
474     /* Return the DMA_IT status */
475     return  bitstatus;
476 }
477 
478 /**
479 * @brief  Clears the DMAy Channelx's interrupt pending bits.
480 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
481 *   This parameter can be any combination (for the same DMA) of
482 *   the following values:
483 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
484 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
485 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
486 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
487 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
488 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
489 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
490 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
491 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
492 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
493 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
494 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
495 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
496 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
497 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
498 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
499 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
500 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
501 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
502 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
503 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
504 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
505 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
506 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
507 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
508 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
509 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
510 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
511 * @retval : None
512 */
DMA_ClearITPendingBit(uint32_t DMA_IT)513 void DMA_ClearITPendingBit(uint32_t DMA_IT)
514 {
515     /* Check the parameters */
516     assert_param(IS_DMA_CLEAR_IT(DMA_IT));
517 
518     /* Clear the selected DMA interrupt pending bits */
519     DMA1->IFCR = DMA_IT;
520 
521 }
522 
523 /**
524 * @}
525 */
526 
527 /**
528 * @}
529 */
530 
531 /**
532 * @}
533 */
534 
535 /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/
536