1 /** 2 ****************************************************************************** 3 * @file HAL_pwr.c 4 * @author AE Team 5 * @version V2.0.0 6 * @date 22/08/2017 7 * @brief This file provides all the PWR firmware functions. 8 ****************************************************************************** 9 * @copy 10 * 11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 * TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY 14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 * 18 * <h2><center>© COPYRIGHT 2017 MindMotion</center></h2> 19 */ 20 21 /* Includes ------------------------------------------------------------------*/ 22 #include "HAL_pwr.h" 23 #include "HAL_rcc.h" 24 25 /** @addtogroup StdPeriph_Driver 26 * @{ 27 */ 28 29 /** @defgroup PWR 30 * @brief PWR driver modules 31 * @{ 32 */ 33 34 /** @defgroup PWR_Private_TypesDefinitions 35 * @{ 36 */ 37 38 /** 39 * @} 40 */ 41 42 /** @defgroup PWR_Private_Defines 43 * @{ 44 */ 45 46 /* --------- PWR registers bit address in the alias region ---------- */ 47 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 48 49 /* --- CR Register ---*/ 50 51 /* Alias word address of DBP bit */ 52 #define CR_OFFSET (PWR_OFFSET + 0x00) 53 #define DBP_BitNumber 0x08 54 #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 55 56 /* Alias word address of PVDE bit */ 57 #define PVDE_BitNumber 0x04 58 #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 59 60 /* --- CSR Register ---*/ 61 62 /* Alias word address of EWUP bit */ 63 #define CSR_OFFSET (PWR_OFFSET + 0x04) 64 #define EWUP_BitNumber 0x08 65 #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 66 67 /* ------------------ PWR registers bit mask ------------------------ */ 68 69 /* CR register bit mask */ 70 #define CR_PDDS_Set ((uint32_t)0x00000002) 71 #define CR_DS_Mask ((uint32_t)0xFFFFFFFC) 72 #define CR_CWUF_Set ((uint32_t)0x00000004) 73 #define CR_PLS_Mask ((uint32_t)0xFFFFE1FF) 74 75 /* --------- Cortex System Control register bit mask ---------------- */ 76 77 /* Cortex System Control register address */ 78 #define SCB_SysCtrl ((uint32_t)0xE000ED10) 79 80 /* SLEEPDEEP bit mask */ 81 #define SysCtrl_SLEEPDEEP_Set ((uint32_t)0x00000004) 82 /** 83 * @} 84 */ 85 86 /** @defgroup PWR_Private_Macros 87 * @{ 88 */ 89 90 /** 91 * @} 92 */ 93 94 /** @defgroup PWR_Private_Variables 95 * @{ 96 */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup PWR_Private_FunctionPrototypes 103 * @{ 104 */ 105 106 /** 107 * @} 108 */ 109 110 /** @defgroup PWR_Private_Functions 111 * @{ 112 */ 113 114 /** 115 * @brief Deinitializes the PWR peripheral registers to their default 116 * reset values. 117 * @param None 118 * @retval : None 119 */ PWR_DeInit(void)120void PWR_DeInit(void) 121 { 122 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 123 RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 124 } 125 126 127 /** 128 * @brief Enables or disables access to the RTC and backup registers. 129 * @param NewState: new state of the access to the RTC and backup 130 * registers. This parameter can be: ENABLE or DISABLE. 131 * @retval : None 132 */ PWR_BackupAccessCmd(FunctionalState NewState)133void PWR_BackupAccessCmd(FunctionalState NewState) 134 { 135 /* Check the parameters */ 136 assert_param(IS_FUNCTIONAL_STATE(NewState)); 137 //*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 138 if(NewState!=DISABLE) 139 { 140 PWR->CR |= 0x00000100; 141 } 142 else 143 { 144 PWR->CR &= 0xfffffeff; 145 } 146 147 } 148 149 /** 150 * @brief Enables or disables the Power Voltage Detector(PVD). 151 * @param NewState: new state of the PVD. 152 * This parameter can be: ENABLE or DISABLE. 153 * @retval : None 154 */ PWR_PVDCmd(FunctionalState NewState)155void PWR_PVDCmd(FunctionalState NewState) 156 { 157 /* Check the parameters */ 158 assert_param(IS_FUNCTIONAL_STATE(NewState)); 159 160 if(NewState==ENABLE) 161 { 162 PWR->CR |= 0x00000010; 163 } 164 else 165 { 166 PWR->CR &= 0xffffffef; 167 } 168 } 169 170 /** 171 * @brief Configures the voltage threshold detected by the Power Voltage 172 * Detector(PVD). 173 * @param PWR_PVDLevel: specifies the PVD detection level 174 * This parameter can be one of the following values: 175 * @arg PWR_PVDLevel_1V8: PVD detection level set to 1.8V 176 * @arg PWR_PVDLevel_2V1: PVD detection level set to 2.1V 177 * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 178 * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 179 * @arg PWR_PVDLevel_3V0: PVD detection level set to 3.0V 180 * @arg PWR_PVDLevel_3V3: PVD detection level set to 3.3V 181 * @arg PWR_PVDLevel_3V6: PVD detection level set to 3.6V 182 * @arg PWR_PVDLevel_3V9: PVD detection level set to 3.9V 183 * @arg PWR_PVDLevel_4V2: PVD detection level set to 4.2V 184 * @arg PWR_PVDLevel_4V5: PVD detection level set to 4.5V 185 * @arg PWR_PVDLevel_4V8: PVD detection level set to 4.8V 186 * @retval : None 187 */ PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)188void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 189 { 190 uint32_t tmpreg = 0; 191 /* Check the parameters */ 192 assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 193 tmpreg = PWR->CR; 194 /* Clear PLS[12:9] bits */ 195 tmpreg &= CR_PLS_Mask; 196 /* Set PLS[12:9] bits according to PWR_PVDLevel value */ 197 tmpreg |= PWR_PVDLevel; 198 /* Store the new value */ 199 PWR->CR = tmpreg; 200 } 201 202 /** 203 * @brief Enables or disables the WakeUp Pin functionality. 204 * @param NewState: new state of the WakeUp Pin functionality. 205 * This parameter can be: ENABLE or DISABLE. 206 * @retval : None 207 */ PWR_WakeUpPinCmd(FunctionalState NewState)208void PWR_WakeUpPinCmd(FunctionalState NewState) 209 { 210 /* Check the parameters */ 211 assert_param(IS_FUNCTIONAL_STATE(NewState)); 212 213 if(NewState!=DISABLE) 214 { 215 PWR->CSR |= 0x00000100; 216 } 217 else 218 { 219 PWR->CSR &= 0xfffffeff; 220 } 221 } 222 223 /** 224 * @brief Enters STOP mode. 225 * @param PWR_Regulator: specifies the regulator state in STOP mode. 226 * This parameter can be one of the following values: 227 * @arg PWR_Regulator_ON: STOP mode with regulator ON 228 * @arg PWR_Regulator_LowPower: STOP mode with 229 * regulator in low power mode 230 * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or 231 * WFE instruction. 232 * This parameter can be one of the following values: 233 * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 234 * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 235 * @retval : None 236 */ PWR_EnterSTOPMode(uint32_t PWR_Regulator,uint8_t PWR_STOPEntry)237void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 238 { 239 uint32_t tmpreg = 0; 240 /* Check the parameters */ 241 assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 242 assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 243 244 /* Select the regulator state in STOP mode ---------------------------------*/ 245 tmpreg = PWR->CR; 246 /* Clear PDDS and LPDS bits */ 247 tmpreg &= CR_DS_Mask; 248 /* Set LPDS bit according to PWR_Regulator value */ 249 tmpreg |= PWR_Regulator; 250 /* Store the new value */ 251 PWR->CR = tmpreg; 252 /* Set SLEEPDEEP bit of Cortex System Control Register */ 253 254 SCB->SCR |= SysCtrl_SLEEPDEEP_Set; 255 /* Select STOP mode entry --------------------------------------------------*/ 256 if(PWR_STOPEntry == PWR_STOPEntry_WFI) 257 { 258 /* Request Wait For Interrupt */ 259 __WFI(); 260 } 261 else 262 { 263 /* Request Wait For Event */ 264 __WFE(); 265 } 266 } 267 268 /** 269 * @brief Enters STANDBY mode. 270 * @param None 271 * @retval : None 272 */ PWR_EnterSTANDBYMode(void)273void PWR_EnterSTANDBYMode(void) 274 { 275 /* Clear Wake-up flag */ 276 PWR->CR |= CR_CWUF_Set; 277 /* Select STANDBY mode */ 278 PWR->CR |= CR_PDDS_Set; 279 /* Set SLEEPDEEP bit of Cortex System Control Register */ 280 SCB->SCR |= SysCtrl_SLEEPDEEP_Set; 281 /* This option is used to ensure that store operations are completed */ 282 #if defined ( __CC_ARM ) 283 __force_stores(); 284 #endif 285 /* Request Wait For Interrupt */ 286 __WFI(); 287 } 288 289 /** 290 * @brief Checks whether the specified PWR flag is set or not. 291 * @param PWR_FLAG: specifies the flag to check. 292 * This parameter can be one of the following values: 293 * @arg PWR_FLAG_WU: Wake Up flag 294 * @arg PWR_FLAG_SB: StandBy flag 295 * @arg PWR_FLAG_PVDO: PVD Output 296 * @retval : The new state of PWR_FLAG (SET or RESET). 297 */ PWR_GetFlagStatus(uint32_t PWR_FLAG)298FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 299 { 300 FlagStatus bitstatus = RESET; 301 /* Check the parameters */ 302 assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 303 304 if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 305 { 306 bitstatus = SET; 307 } 308 else 309 { 310 bitstatus = RESET; 311 } 312 /* Return the flag status */ 313 return bitstatus; 314 } 315 316 /** 317 * @brief Clears the PWR's pending flags. 318 * @param PWR_FLAG: specifies the flag to clear. 319 * This parameter can be one of the following values: 320 * @arg PWR_FLAG_WU: Wake Up flag 321 * @arg PWR_FLAG_SB: StandBy flag 322 * @retval : None 323 */ PWR_ClearFlag(uint32_t PWR_FLAG)324void PWR_ClearFlag(uint32_t PWR_FLAG) 325 { 326 /* Check the parameters */ 327 assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 328 329 PWR->CR |= PWR_FLAG << 2; 330 } 331 332 /** 333 * @} 334 */ 335 336 /** 337 * @} 338 */ 339 340 /** 341 * @} 342 */ 343 344 /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/ 345