1 /**
2 ******************************************************************************
3 * @file system_MM32L0xx.c
4 * @author AE Team
5 * @version V2.0.0
6 * @date 22/08/2017
7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
8 *
9 * 1. This file provides two functions and one global variable to be called from
10 * user application:
11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
12 * factors, AHB/APBx prescalers and Flash settings).
13 * This function is called at startup just after reset and
14 * before branch to main program. This call is made inside
15 * the "startup_MM32x031_xx.s" file.
16 *
17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
18 * by the user application to setup the SysTick
19 * timer or configure other parameters.
20 *
21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
22 * be called whenever the core clock is changed
23 * during program execution.
24 *
25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
26 * Then SystemInit() function is called, in "system_MM32L0xx.s" file, to
27 * configure the system clock before to branch to main program.
28 *
29 * 3. If the system clock source selected by user fails to startup, the SystemInit()
30 * function will do nothing and HSI still used as system clock source. User can
31 * add some code to deal with this issue inside the SetSysClock() function.
32 *
33 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
34 * the product used), refer to "HSE_VALUE" define in "MM32L073.h" file.
35 * When HSE is used as system clock source, directly or through PLL, and you
36 * are using different crystal you have to adapt the HSE value to your own
37 * configuration.
38 *
39 ******************************************************************************
40 * @attention
41 *
42 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
43 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
44 * TIME. AS A RESULT, MINDMOTION SHALL NOT BE HELD LIABLE FOR ANY
45 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
46 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
47 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
48 *
49 ******************************************************************************
50 */
51
52 /** @addtogroup CMSIS
53 * @{
54 */
55 #include "HAL_device.h"
56
57
58 /**
59 * @}
60 */
61
62 /**
63 * @}
64 */
65
66 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
67 frequency (after reset the HSI is used as SYSCLK source)
68
69 IMPORTANT NOTE:
70 ==============
71 1. After each device reset the HSI is used as System clock source.
72
73 2. Please make sure that the selected System clock doesn't exceed your device's
74 maximum frequency.
75
76 3. If none of the define below is enabled, the HSI is used as System clock
77 source.
78
79 4. The System clock configuration functions provided within this file assume that:
80 - For Low, Medium and High density Value line devices an external 8MHz
81 crystal is used to drive the System clock.
82 - For Low, Medium and High density devices an external 8MHz crystal is
83 used to drive the System clock.
84 - For Connectivity line devices an external 25MHz crystal is used to drive
85 the System clock.
86 If you are using different crystal you have to adapt those functions accordingly.
87 */
88
89 //#define SYSCLK_FREQ_HSE HSE_VALUE
90 //#define SYSCLK_FREQ_24MHz 24000000
91 //#define SYSCLK_FREQ_36MHz 36000000
92 //#define SYSCLK_FREQ_48MHz 48000000
93
94 //#define SYSCLK_HSI_24MHz 24000000
95 //#define SYSCLK_HSI_36MHz 36000000
96 #define SYSCLK_HSI_48MHz 48000000
97
98
99 /*!< Uncomment the following line if you need to relocate your vector Table in
100 Internal SRAM. */
101 /* #define VECT_TAB_SRAM */
102 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
103 This value must be a multiple of 0x200. */
104
105 /**
106 * @}
107 */
108
109 /*******************************************************************************
110 * Clock Definitions
111 *******************************************************************************/
112 #ifdef SYSCLK_FREQ_HSE
113 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
114 #elif defined SYSCLK_FREQ_24MHz
115 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
116 #elif defined SYSCLK_FREQ_36MHz
117 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
118 #elif defined SYSCLK_FREQ_48MHz
119 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
120
121 #elif defined SYSCLK_HSI_24MHz
122 uint32_t SystemCoreClock = SYSCLK_HSI_24MHz; /*!< System Clock Frequency (Core Clock) */
123 #elif defined SYSCLK_HSI_36MHz
124 uint32_t SystemCoreClock = SYSCLK_HSI_36MHz; /*!< System Clock Frequency (Core Clock) */
125 #elif defined SYSCLK_HSI_48MHz
126 uint32_t SystemCoreClock = SYSCLK_HSI_48MHz; /*!< System Clock Frequency (Core Clock) */
127
128 #else /*!< HSI Selected as System Clock source */
129 uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
130 #endif
131
132 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
133 /**
134 * @}
135 */
136
137 static void SetSysClock(void);
138
139 #ifdef SYSCLK_FREQ_HSE
140 static void SetSysClockToHSE(void);
141 #elif defined SYSCLK_FREQ_24MHz
142 static void SetSysClockTo24(void);
143 #elif defined SYSCLK_FREQ_36MHz
144 static void SetSysClockTo36(void);
145 #elif defined SYSCLK_FREQ_48MHz
146 static void SetSysClockTo48(void);
147
148 #elif defined SYSCLK_HSI_24MHz
149 static void SetSysClockTo24_HSI(void);
150 #elif defined SYSCLK_HSI_36MHz
151 static void SetSysClockTo36_HSI(void);
152 #elif defined SYSCLK_HSI_48MHz
153 static void SetSysClockTo48_HSI(void);
154
155 #endif
156
157 #ifdef DATA_IN_ExtSRAM
158 static void SystemInit_ExtMemCtl(void);
159 #endif /* DATA_IN_ExtSRAM */
160
161 /**
162 * @}
163 */
164
165 /**
166 * @brief Setup the microcontroller system
167 * Initialize the Embedded Flash Interface, the PLL and update the
168 * SystemCoreClock variable.
169 * @note This function should be used only after reset.
170 * @param None
171 * @retval None
172 */
SystemInit(void)173 void SystemInit (void)
174 {
175 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
176 /* Set HSION bit */
177 RCC->CR |= (uint32_t)0x1;
178
179
180 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
181 RCC->CFGR &= (uint32_t)0xF8FFC00C;
182
183 /* Reset HSEON, CSSON and PLLON bits */
184 RCC->CR &= (uint32_t)0xFEF6FFFF;
185
186 /* Reset HSEBYP bit */
187 RCC->CR &= (uint32_t)0xFFFBFFFF;
188
189 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
190 RCC->CFGR &= (uint32_t)0xFF3CFFFF;
191 RCC->CR &= (uint32_t)0x008FFFFF;
192
193 /* Disable all interrupts and clear pending bits */
194 RCC->CIR &= 0xFF62E262;
195
196 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
197 /* Configure the Flash Latency cycles and enable prefetch buffer */
198
199 SetSysClock();
200
201 }
202
203 /**
204 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
205 * @param None
206 * @retval None
207 */
SetSysClock(void)208 static void SetSysClock(void)
209 {
210 #ifdef SYSCLK_FREQ_HSE
211 SetSysClockToHSE();
212 #elif defined SYSCLK_FREQ_24MHz
213 SetSysClockTo24();
214 #elif defined SYSCLK_FREQ_36MHz
215 SetSysClockTo36();
216 #elif defined SYSCLK_FREQ_48MHz
217 SetSysClockTo48();
218
219 #elif defined SYSCLK_HSI_24MHz
220 SetSysClockTo24_HSI();
221 #elif defined SYSCLK_HSI_36MHz
222 SetSysClockTo36_HSI();
223 #elif defined SYSCLK_HSI_48MHz
224 SetSysClockTo48_HSI();
225 #endif
226
227 /* If none of the define above is enabled, the HSI is used as System clock
228 source (default after reset) */
229 }
230
231 #ifdef SYSCLK_FREQ_HSE
232 /**
233 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
234 * and PCLK1 prescalers.
235 * @note This function should be used only after reset.
236 * @param None
237 * @retval None
238 */
SetSysClockToHSE(void)239 static void SetSysClockToHSE(void)
240 {
241 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
242 int nTime = 2;
243 u16 i = 0;
244
245 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
246 /* Enable HSE */
247 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
248
249 /* Wait till HSE is ready and if Time out is reached exit */
250 do
251 {
252 HSEStatus = RCC->CR & RCC_CR_HSERDY;
253 StartUpCounter++;
254 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
255
256 /* Software delay needs more than 2ms */
257 while(nTime--)
258 {
259 i = 750;
260 while(i--);
261 }
262
263 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
264 {
265 HSEStatus = (uint32_t)0x01;
266 }
267 else
268 {
269 HSEStatus = (uint32_t)0x00;
270 }
271
272 if (HSEStatus == (uint32_t)0x01)
273 {
274 /* Enable Prefetch Buffer */
275 FLASH->ACR |= FLASH_ACR_PRFTBE;
276
277 /* Flash 0 wait state ,bit0~2*/
278 FLASH->ACR &= ~0x07;
279 /* HCLK = SYSCLK */
280 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
281
282 /* PCLK2 = HCLK */
283 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
284
285 /* PCLK1 = HCLK */
286 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
287
288 /* Select HSE as system clock source */
289 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
290 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
291
292 /* Wait till HSE is used as system clock source */
293 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
294 {
295 }
296 }
297 else
298 { /* If HSE fails to start-up, the application will have wrong clock
299 configuration. User can add here some code to deal with this error */
300 }
301 }
302 #elif defined SYSCLK_FREQ_24MHz
303 /**
304 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
305 * and PCLK1 prescalers.
306 * @note This function should be used only after reset.
307 * @param None
308 * @retval None
309 */
SetSysClockTo24(void)310 static void SetSysClockTo24(void)
311 {
312 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
313 int nTime = 2;
314 u16 i = 0;
315
316 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
317 /* Enable HSE */
318 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
319
320 /* Wait till HSE is ready and if Time out is reached exit */
321 do
322 {
323 HSEStatus = RCC->CR & RCC_CR_HSERDY;
324 StartUpCounter++;
325 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
326
327 /* Software delay needs more than 2ms */
328 while(nTime--)
329 {
330 i = 750;
331 while(i--);
332 }
333
334 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
335 {
336 HSEStatus = (uint32_t)0x01;
337 }
338 else
339 {
340 HSEStatus = (uint32_t)0x00;
341 }
342
343 if (HSEStatus == (uint32_t)0x01)
344 {
345 /* Enable Prefetch Buffer */
346 FLASH->ACR |= FLASH_ACR_PRFTBE;
347 /* Flash 0 wait state ,bit0~2*/
348 FLASH->ACR &= ~0x07;
349 FLASH->ACR |= 0x01;
350 /* HCLK = SYSCLK */
351 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
352
353 /* PCLK2 = HCLK */
354 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
355
356 /* PCLK1 = HCLK */
357 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
358
359 /* PLL configuration: = (HSE ) * (2+1) = 24 MHz */
360 RCC->CFGR &= (uint32_t)0xFFFCFFFF;
361 RCC->CR &= (uint32_t)0x000FFFFF;
362
363 RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ;
364 RCC->CR |= 0x08000000;//pll=3/1
365
366 /* Enable PLL */
367 RCC->CR |= RCC_CR_PLLON;
368
369 /* Wait till PLL is ready */
370 while((RCC->CR & RCC_CR_PLLRDY) == 0)
371 {
372 }
373
374 /* Select PLL as system clock source */
375 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
376 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
377
378 /* Wait till PLL is used as system clock source */
379 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
380 {
381 }
382 }
383 else
384 { /* If HSE fails to start-up, the application will have wrong clock
385 configuration. User can add here some code to deal with this error */
386 }
387 }
388 #elif defined SYSCLK_FREQ_36MHz
389 /**
390 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
391 * and PCLK1 prescalers.
392 * @note This function should be used only after reset.
393 * @param None
394 * @retval None
395 */
SetSysClockTo36(void)396 static void SetSysClockTo36(void)
397 {
398 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
399 int nTime = 2;
400 u16 i = 0;
401
402 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
403 /* Enable HSE */
404 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
405
406 /* Wait till HSE is ready and if Time out is reached exit */
407 do
408 {
409 HSEStatus = RCC->CR & RCC_CR_HSERDY;
410 StartUpCounter++;
411 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
412
413 /* Software delay needs more than 2ms */
414 while(nTime--)
415 {
416 i = 750;
417 while(i--);
418 }
419
420 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
421 {
422 HSEStatus = (uint32_t)0x01;
423 }
424 else
425 {
426 HSEStatus = (uint32_t)0x00;
427 }
428
429 if (HSEStatus == (uint32_t)0x01)
430 {
431 /* Enable Prefetch Buffer */
432 FLASH->ACR |= FLASH_ACR_PRFTBE;
433
434 /* Flash 0 wait state ,bit0~2*/
435 FLASH->ACR &= ~0x07;
436 FLASH->ACR |= 0x01;
437 /* HCLK = SYSCLK */
438 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
439
440 /* PCLK2 = HCLK */
441 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
442
443 /* PCLK1 = HCLK */
444 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
445
446 /* PLL configuration: = (HSE ) * (8+1)/(1+1) = 36 MHz */
447 RCC->CFGR &= (uint32_t)0xFFFCFFFF;
448 RCC->CR &= (uint32_t)0x000FFFFF;
449
450 RCC->CFGR |= (uint32_t)RCC_CFGR_PLLSRC ;
451 RCC->CR |= 0x20100000;//pll = 9/2
452
453 /* Enable PLL */
454 RCC->CR |= RCC_CR_PLLON;
455
456 /* Wait till PLL is ready */
457 while((RCC->CR & RCC_CR_PLLRDY) == 0)
458 {
459 }
460
461 /* Select PLL as system clock source */
462 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
463 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
464
465 /* Wait till PLL is used as system clock source */
466 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
467 {
468 }
469 }
470 else
471 { /* If HSE fails to start-up, the application will have wrong clock
472 configuration. User can add here some code to deal with this error */
473 }
474 }
475 #elif defined SYSCLK_FREQ_48MHz
476 /**
477 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
478 * and PCLK1 prescalers.
479 * @note This function should be used only after reset.
480 * @param None
481 * @retval None
482 */
SetSysClockTo48(void)483 static void SetSysClockTo48(void)
484 {
485 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
486 int nTime = 2;
487 u16 i = 0;
488
489 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
490 /* Enable HSE */
491 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
492
493 /* Wait till HSE is ready and if Time out is reached exit */
494 do
495 {
496 HSEStatus = RCC->CR & RCC_CR_HSERDY;
497 StartUpCounter++;
498 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
499
500 /* Software delay needs more than 2ms */
501 while(nTime--)
502 {
503 i = 750;
504 while(i--);
505 }
506
507 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
508 {
509 HSEStatus = (uint32_t)0x01;
510 }
511 else
512 {
513 HSEStatus = (uint32_t)0x00;
514 }
515
516 if (HSEStatus == (uint32_t)0x01)
517 {
518 /* Enable Prefetch Buffer */
519 FLASH->ACR |= FLASH_ACR_PRFTBE;
520 /* Flash 0 wait state ,bit0~2*/
521 FLASH->ACR &= ~0x07;
522 FLASH->ACR |=0x02;
523 /* HCLK = SYSCLK */
524 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
525
526 /* PCLK2 = HCLK */
527 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
528
529 /* PCLK1 = HCLK */
530 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
531
532 /* PLL configuration: = (HSE ) * (5+1) = 48MHz */
533 RCC->CFGR &= (uint32_t)0xFFFCFFFF;
534 RCC->CR &= (uint32_t)0x000FFFFF;
535
536 RCC->CFGR |= (uint32_t ) RCC_CFGR_PLLSRC ;
537 RCC->CR |= 0x14000000;//pll = 6/1
538
539 /* Enable PLL */
540 RCC->CR |= RCC_CR_PLLON;
541
542 /* Wait till PLL is ready */
543 while((RCC->CR & RCC_CR_PLLRDY) == 0)
544 {
545 }
546
547 /* Select PLL as system clock source */
548 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
549 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
550
551 /* Wait till PLL is used as system clock source */
552 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
553 {
554 }
555 }
556 else
557 { /* If HSE fails to start-up, the application will have wrong clock
558 configuration. User can add here some code to deal with this error */
559 }
560 }
561
562 #elif defined SYSCLK_HSI_24MHz
SetSysClockTo24_HSI()563 void SetSysClockTo24_HSI()
564 {
565 unsigned char temp=0;
566
567 RCC->CR|=RCC_CR_HSION;
568 while(!(RCC->CR&RCC_CR_HSIRDY));
569 RCC->CFGR=RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
570
571 RCC->CFGR&=~RCC_CFGR_PLLSRC; //PLLSRC ON
572
573 RCC->CR &=~(RCC_CR_PLLON); //��PLL// RCC->CR &=~(7<<20); //��PLL
574
575 RCC->CR &=~(0x1f<<26);
576 RCC->CR|=(2 - 1) << 26; //����PLLֵ 2~16
577
578 FLASH->ACR=FLASH_ACR_PRFTBE; //FLASH 0����ʱ����
579
580 RCC->CR|=RCC_CR_PLLON; //PLLON
581 while(!(RCC->CR&RCC_CR_PLLRDY));//�ȴ�PLL����
582 RCC->CFGR&=~RCC_CFGR_SW;
583 RCC->CFGR|=RCC_CFGR_SW_PLL;//PLL��Ϊϵͳʱ��
584 while(temp!=0x02) //�ȴ�PLL��Ϊϵͳʱ�����óɹ�
585 {
586 temp=RCC->CFGR>>2;
587 temp&=0x03;
588 }
589 }
590
591 #elif defined SYSCLK_HSI_36MHz
SetSysClockTo36_HSI()592 void SetSysClockTo36_HSI()
593 {
594 unsigned char temp=0;
595
596 RCC->CR|=RCC_CR_HSION;
597 while(!(RCC->CR&RCC_CR_HSIRDY));
598 RCC->CFGR=RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
599
600 RCC->CFGR&=~RCC_CFGR_PLLSRC; //PLLSRC ON
601
602 RCC->CR &=~(RCC_CR_PLLON); //��PLL// RCC->CR &=~(7<<20); //��PLL
603
604 RCC->CR &=~(0x1f<<26);
605 RCC->CR|=(3 - 1) << 26; //����PLLֵ 2~16
606
607 FLASH->ACR=FLASH_ACR_LATENCY_1|FLASH_ACR_PRFTBE; //FLASH 1����ʱ����
608
609 RCC->CR|=RCC_CR_PLLON; //PLLON
610 while(!(RCC->CR&RCC_CR_PLLRDY));//�ȴ�PLL����
611 RCC->CFGR&=~RCC_CFGR_SW;
612 RCC->CFGR|=RCC_CFGR_SW_PLL;//PLL��Ϊϵͳʱ��
613 while(temp!=0x02) //�ȴ�PLL��Ϊϵͳʱ�����óɹ�
614 {
615 temp=RCC->CFGR>>2;
616 temp&=0x03;
617 }
618 }
619
620 #elif defined SYSCLK_HSI_48MHz
SetSysClockTo48_HSI()621 void SetSysClockTo48_HSI()
622 {
623 unsigned char temp=0;
624
625 RCC->CR|=RCC_CR_HSION;
626 while(!(RCC->CR&RCC_CR_HSIRDY));
627 RCC->CFGR=RCC_CFGR_PPRE1_2; //APB1=DIV2;APB2=DIV1;AHB=DIV1;
628
629 RCC->CFGR&=~RCC_CFGR_PLLSRC; //PLLSRC ON
630
631 RCC->CR &=~(RCC_CR_PLLON); //��PLL// RCC->CR &=~(7<<20); //��PLL
632
633 RCC->CR &=~(0x1f<<26);
634 RCC->CR|=(4 - 1) << 26; //����PLLֵ 2~16
635
636 FLASH->ACR=FLASH_ACR_LATENCY_1|FLASH_ACR_PRFTBE; //FLASH 1����ʱ����
637
638 RCC->CR|=RCC_CR_PLLON; //PLLON
639 while(!(RCC->CR&RCC_CR_PLLRDY));//�ȴ�PLL����
640 RCC->CFGR&=~RCC_CFGR_SW;
641 RCC->CFGR|=RCC_CFGR_SW_PLL;//PLL��Ϊϵͳʱ��
642 while(temp!=0x02) //�ȴ�PLL��Ϊϵͳʱ�����óɹ�
643 {
644 temp=RCC->CFGR>>2;
645 temp&=0x03;
646 }
647 }
648
649 #endif
650
651 /**
652 * @}
653 */
654
655 /**
656 * @}
657 */
658
659 /**
660 * @}
661 */
662 /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/
663