1 /** 2 ****************************************************************************** 3 * @file HAL_rcc.h 4 * @author AE Team 5 * @version V1.0.0 6 * @date 28/7/2017 7 * @brief This file contains all the functions prototypes for the RCC firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2017 MindMotion</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __HAL_RCC_H 24 #define __HAL_RCC_H 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "HAL_device.h" 28 29 /** @addtogroup StdPeriph_Driver 30 * @{ 31 */ 32 33 /** @addtogroup RCC 34 * @{ 35 */ 36 37 /** @defgroup RCC_Exported_Types 38 * @{ 39 */ 40 41 typedef struct 42 { 43 uint32_t SYSCLK_Frequency; 44 uint32_t HCLK_Frequency; 45 uint32_t PCLK1_Frequency; 46 uint32_t PCLK2_Frequency; 47 uint32_t ADCCLK_Frequency; 48 }RCC_ClocksTypeDef; 49 50 /** 51 * @} 52 */ 53 54 /** @defgroup RCC_Exported_Constants 55 * @{ 56 */ 57 58 /** @defgroup HSE_configuration 59 * @{ 60 */ 61 62 #define RCC_HSE_OFF ((uint32_t)0x00000000) 63 #define RCC_HSE_ON ((uint32_t)0x00010000) 64 #define RCC_HSE_Bypass ((uint32_t)0x00040000) 65 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 66 ((HSE) == RCC_HSE_Bypass)) 67 68 /** 69 * @} 70 */ 71 72 /** @defgroup PLL_entry_clock_source 73 * @{ 74 */ 75 76 #define RCC_PLLSource_HSI_Div4 ((uint32_t)0x00000000) 77 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) 78 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) 79 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div4) || \ 80 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 81 ((SOURCE) == RCC_PLLSource_HSE_Div2)) 82 /** 83 * @} 84 */ 85 86 87 /** @defgroup System_clock_source 88 * @{ 89 */ 90 91 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 92 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 93 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 94 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 95 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 96 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 97 /** 98 * @} 99 */ 100 101 /** @defgroup AHB_clock_source 102 * @{ 103 */ 104 105 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 106 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 107 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 108 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 109 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 110 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 111 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 112 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 113 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 114 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 115 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 116 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 117 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 118 ((HCLK) == RCC_SYSCLK_Div512)) 119 /** 120 * @} 121 */ 122 123 /** @defgroup APB1_APB2_clock_source 124 * @{ 125 */ 126 127 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 128 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 129 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 130 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 131 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 132 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 133 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 134 ((PCLK) == RCC_HCLK_Div16)) 135 136 /** 137 * @} 138 */ 139 140 /** @defgroup PLL_multiplication_factor 141 * @{ 142 */ 143 144 #define RCC_PLLMul_2 ((uint32_t)0x00000000) 145 #define RCC_PLLMul_3 ((uint32_t)0x00040000) 146 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 147 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 148 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 149 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 150 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 151 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 152 #define RCC_PLLMul_10 ((uint32_t)0x00200000) 153 #define RCC_PLLMul_11 ((uint32_t)0x00240000) 154 #define RCC_PLLMul_12 ((uint32_t)0x00280000) 155 #define RCC_PLLMul_13 ((uint32_t)0x002C0000) 156 #define RCC_PLLMul_14 ((uint32_t)0x00300000) 157 #define RCC_PLLMul_15 ((uint32_t)0x00340000) 158 #define RCC_PLLMul_16 ((uint32_t)0x00380000) 159 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 160 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 161 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 162 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 163 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 164 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 165 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 166 ((MUL) == RCC_PLLMul_16)) 167 168 169 /** 170 * @} 171 */ 172 173 /** @defgroup RCC_Interrupt_source 174 * @{ 175 */ 176 177 #define RCC_IT_LSIRDY ((uint8_t)0x01) 178 #define RCC_IT_LSERDY ((uint8_t)0x02) 179 #define RCC_IT_HSIRDY ((uint8_t)0x04) 180 #define RCC_IT_HSERDY ((uint8_t)0x08) 181 #define RCC_IT_PLLRDY ((uint8_t)0x10) 182 #define RCC_IT_CSS ((uint8_t)0x80) 183 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 184 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 185 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 186 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 187 188 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 189 /** 190 * @} 191 */ 192 193 /** @defgroup USB_clock_source 194 * @{ 195 */ 196 197 198 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x00) 199 #define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01) 200 #define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02) 201 #define RCC_USBCLKSource_PLLCLK_Div4 ((uint8_t)0x03) 202 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1) || \ 203 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div2)) 204 /** 205 * @} 206 */ 207 208 /** @defgroup ADC_clock_source 209 * @{ 210 */ 211 212 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) 213 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) 214 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) 215 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) 216 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ 217 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) 218 /** 219 * @} 220 */ 221 222 /** @defgroup LSE_configuration 223 * @{ 224 */ 225 226 #define RCC_LSE_OFF ((uint8_t)0x00) 227 #define RCC_LSE_ON ((uint8_t)0x01) 228 #define RCC_LSE_Bypass ((uint8_t)0x04) 229 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 230 ((LSE) == RCC_LSE_Bypass)) 231 /** 232 * @} 233 */ 234 235 /** @defgroup RTC_clock_source 236 * @{ 237 */ 238 239 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 240 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 241 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) 242 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 243 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 244 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) 245 /** 246 * @} 247 */ 248 249 /** @defgroup AHB_peripheral 250 * @{ 251 */ 252 253 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) 254 //#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) 255 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 256 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) 257 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) 258 #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) 259 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) 260 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) 261 /** 262 * @} 263 */ 264 265 /** @defgroup APB2_peripheral 266 * @{ 267 */ 268 269 #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) 270 #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) 271 #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) 272 #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) 273 #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) 274 #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) 275 #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) 276 #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) 277 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) 278 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) 279 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) 280 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 281 282 #define RCC_APB2Periph_UART1 ((uint32_t)0x00004000) 283 #define RCC_APB2Periph_ALL ((uint32_t)0x0003FFFD) 284 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFC0002) == 0x00) && ((PERIPH) != 0x00)) 285 /** 286 * @} 287 */ 288 289 /** @defgroup APB1_peripheral 290 * @{ 291 */ 292 293 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 294 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 295 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 296 297 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 298 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 299 300 #define RCC_APB1Periph_UART2 ((uint32_t)0x00020000) 301 #define RCC_APB1Periph_UART3 ((uint32_t)0x00040000) 302 303 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 304 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 305 #define RCC_APB1Periph_USB ((uint32_t)0x00800000) 306 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 307 #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) 308 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 309 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 310 #define RCC_APB1Periph_ALL ((uint32_t)0x3AFEC83F) 311 312 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC50137C0) == 0x00) && ((PERIPH) != 0x00)) 313 /** 314 * @} 315 */ 316 317 /** @defgroup Clock_source_to_output_on_MCO_pin 318 * @{ 319 */ 320 321 #define RCC_MCO_NoClock ((uint8_t)0x00) 322 #define RCC_MCO_SYSCLK ((uint8_t)0x04) 323 #define RCC_MCO_HSI ((uint8_t)0x05) 324 #define RCC_MCO_HSE ((uint8_t)0x06) 325 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) 326 #define RCC_MCO_LSI ((uint8_t)0x02) 327 #define RCC_MCO_LSE ((uint8_t)0x03) 328 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 329 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 330 ((MCO) == RCC_MCO_PLLCLK_Div2)||((MCO) == RCC_MCO_LSI)||\ 331 ((MCO) == RCC_MCO_LSE)) 332 /** 333 * @} 334 */ 335 336 /** @defgroup RCC_Flag 337 * @{ 338 */ 339 340 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 341 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 342 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 343 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 344 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 345 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 346 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 347 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 348 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 349 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 350 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 351 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 352 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 353 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 354 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 355 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 356 ((FLAG) == RCC_FLAG_LPWRRST)) 357 358 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 359 /** 360 * @} 361 */ 362 363 /** 364 * @} 365 */ 366 367 /** @defgroup RCC_Exported_Macros 368 * @{ 369 */ 370 371 /** 372 * @} 373 */ 374 375 /** @defgroup RCC_Exported_Functions 376 * @{ 377 */ 378 379 void RCC_DeInit(void); 380 void RCC_HSEConfig(uint32_t RCC_HSE); 381 ErrorStatus RCC_WaitForHSEStartUp(void); 382 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 383 void RCC_HSICmd(FunctionalState NewState); 384 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 385 void RCC_PLLCmd(FunctionalState NewState); 386 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 387 uint8_t RCC_GetSYSCLKSource(void); 388 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 389 void RCC_PCLK1Config(uint32_t RCC_HCLK); 390 void RCC_PCLK2Config(uint32_t RCC_HCLK); 391 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 392 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); 393 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); 394 void RCC_LSEConfig(uint8_t RCC_LSE); 395 void RCC_LSICmd(FunctionalState NewState); 396 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 397 void RCC_RTCCLKCmd(FunctionalState NewState); 398 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 399 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 400 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 401 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 402 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 403 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 404 void RCC_BackupResetCmd(FunctionalState NewState); 405 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 406 void RCC_MCOConfig(uint8_t RCC_MCO); 407 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 408 void RCC_ClearFlag(void); 409 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 410 void RCC_ClearITPendingBit(uint8_t RCC_IT); 411 412 #endif /* __HAL_RCC_H */ 413 /** 414 * @} 415 */ 416 417 /** 418 * @} 419 */ 420 421 /** 422 * @} 423 */ 424 425 /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/ 426