1 /** 2 ****************************************************************************** 3 * @file HAL_tim.h 4 * @author AE Team 5 * @version V1.0.0 6 * @date 28/7/2017 7 * @brief This file contains all the functions prototypes for the TIM firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2017 MindMotion</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __HAL_TIM_H 24 #define __HAL_TIM_H 25 26 /* Includes ------------------------------------------------------------------*/ 27 #include "HAL_device.h" 28 29 /** @addtogroup StdPeriph_Driver 30 * @{ 31 */ 32 33 /** @addtogroup TIM 34 * @{ 35 */ 36 37 /** @defgroup TIM_Exported_Types 38 * @{ 39 */ 40 41 /** 42 * @brief TIM Time Base Init structure definition 43 */ 44 45 typedef struct 46 { 47 uint16_t TIM_Prescaler; 48 uint16_t TIM_CounterMode; 49 uint16_t TIM_Period; 50 uint16_t TIM_ClockDivision; 51 uint8_t TIM_RepetitionCounter; 52 } TIM_TimeBaseInitTypeDef; 53 54 /** 55 * @brief TIM Output Compare Init structure definition 56 */ 57 58 typedef struct 59 { 60 uint16_t TIM_OCMode; 61 uint16_t TIM_OutputState; 62 uint16_t TIM_OutputNState; 63 uint16_t TIM_Pulse; 64 uint16_t TIM_OCPolarity; 65 uint16_t TIM_OCNPolarity; 66 uint16_t TIM_OCIdleState; 67 uint16_t TIM_OCNIdleState; 68 } TIM_OCInitTypeDef; 69 70 /** 71 * @brief TIM Input Capture Init structure definition 72 */ 73 74 typedef struct 75 { 76 uint16_t TIM_Channel; 77 uint16_t TIM_ICPolarity; 78 uint16_t TIM_ICSelection; 79 uint16_t TIM_ICPrescaler; 80 uint16_t TIM_ICFilter; 81 } TIM_ICInitTypeDef; 82 83 /** 84 * @brief BDTR structure definition 85 */ 86 87 typedef struct 88 { 89 uint16_t TIM_OSSRState; 90 uint16_t TIM_OSSIState; 91 uint16_t TIM_LOCKLevel; 92 uint16_t TIM_DeadTime; 93 uint16_t TIM_Break; 94 uint16_t TIM_BreakPolarity; 95 uint16_t TIM_AutomaticOutput; 96 } TIM_BDTRInitTypeDef; 97 98 /** @defgroup TIM_Exported_constants 99 * @{ 100 */ 101 102 #define IS_TIM_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \ 103 ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \ 104 ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ 105 ((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) 106 107 #define IS_TIM_18_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE)) 108 #define IS_TIM_123458_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || \ 109 ((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || \ 110 ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ 111 ((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) 112 113 /** 114 * @} 115 */ 116 117 /** @defgroup TIM_Output_Compare_and_PWM_modes 118 * @{ 119 */ 120 121 #define TIM_OCMode_Timing ((uint16_t)0x0000) 122 #define TIM_OCMode_Active ((uint16_t)0x0010) 123 #define TIM_OCMode_Inactive ((uint16_t)0x0020) 124 #define TIM_OCMode_Toggle ((uint16_t)0x0030) 125 #define TIM_OCMode_PWM1 ((uint16_t)0x0060) 126 #define TIM_OCMode_PWM2 ((uint16_t)0x0070) 127 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 128 ((MODE) == TIM_OCMode_Active) || \ 129 ((MODE) == TIM_OCMode_Inactive) || \ 130 ((MODE) == TIM_OCMode_Toggle)|| \ 131 ((MODE) == TIM_OCMode_PWM1) || \ 132 ((MODE) == TIM_OCMode_PWM2)) 133 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 134 ((MODE) == TIM_OCMode_Active) || \ 135 ((MODE) == TIM_OCMode_Inactive) || \ 136 ((MODE) == TIM_OCMode_Toggle)|| \ 137 ((MODE) == TIM_OCMode_PWM1) || \ 138 ((MODE) == TIM_OCMode_PWM2) || \ 139 ((MODE) == TIM_ForcedAction_Active) || \ 140 ((MODE) == TIM_ForcedAction_InActive)) 141 /** 142 * @} 143 */ 144 145 /** @defgroup TIM_One_Pulse_Mode 146 * @{ 147 */ 148 149 #define TIM_OPMode_Single ((uint16_t)0x0008) 150 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 151 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 152 ((MODE) == TIM_OPMode_Repetitive)) 153 /** 154 * @} 155 */ 156 157 /** @defgroup TIM_Channel 158 * @{ 159 */ 160 161 #define TIM_Channel_1 ((uint16_t)0x0000) 162 #define TIM_Channel_2 ((uint16_t)0x0004) 163 #define TIM_Channel_3 ((uint16_t)0x0008) 164 #define TIM_Channel_4 ((uint16_t)0x000C) 165 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 166 ((CHANNEL) == TIM_Channel_2) || \ 167 ((CHANNEL) == TIM_Channel_3) || \ 168 ((CHANNEL) == TIM_Channel_4)) 169 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 170 ((CHANNEL) == TIM_Channel_2)) 171 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 172 ((CHANNEL) == TIM_Channel_2) || \ 173 ((CHANNEL) == TIM_Channel_3)) 174 /** 175 * @} 176 */ 177 178 /** @defgroup TIM_Clock_Division_CKD 179 * @{ 180 */ 181 182 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 183 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 184 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 185 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 186 ((DIV) == TIM_CKD_DIV2) || \ 187 ((DIV) == TIM_CKD_DIV4)) 188 /** 189 * @} 190 */ 191 192 /** @defgroup TIM_Counter_Mode 193 * @{ 194 */ 195 196 #define TIM_CounterMode_Up ((uint16_t)0x0000) 197 #define TIM_CounterMode_Down ((uint16_t)0x0010) 198 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 199 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 200 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 201 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 202 ((MODE) == TIM_CounterMode_Down) || \ 203 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 204 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 205 ((MODE) == TIM_CounterMode_CenterAligned3)) 206 /** 207 * @} 208 */ 209 210 /** @defgroup TIM_Output_Compare_Polarity 211 * @{ 212 */ 213 214 #define TIM_OCPolarity_High ((uint16_t)0x0000) 215 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 216 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 217 ((POLARITY) == TIM_OCPolarity_Low)) 218 /** 219 * @} 220 */ 221 222 /** @defgroup TIM_Output_Compare_N_Polarity 223 * @{ 224 */ 225 226 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 227 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 228 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 229 ((POLARITY) == TIM_OCNPolarity_Low)) 230 /** 231 * @} 232 */ 233 234 /** @defgroup TIM_Output_Compare_states 235 * @{ 236 */ 237 238 #define TIM_OutputState_Disable ((uint16_t)0x0000) 239 #define TIM_OutputState_Enable ((uint16_t)0x0001) 240 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 241 ((STATE) == TIM_OutputState_Enable)) 242 /** 243 * @} 244 */ 245 246 /** @defgroup TIM_Output_Compare_N_States 247 * @{ 248 */ 249 250 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 251 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 252 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 253 ((STATE) == TIM_OutputNState_Enable)) 254 /** 255 * @} 256 */ 257 258 /** @defgroup TIM_Capture_Compare_States 259 * @{ 260 */ 261 262 #define TIM_CCx_Enable ((uint16_t)0x0001) 263 #define TIM_CCx_Disable ((uint16_t)0x0000) 264 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 265 ((CCX) == TIM_CCx_Disable)) 266 /** 267 * @} 268 */ 269 270 /** @defgroup TIM_Capture_Compare_N_States 271 * @{ 272 */ 273 274 #define TIM_CCxN_Enable ((uint16_t)0x0004) 275 #define TIM_CCxN_Disable ((uint16_t)0x0000) 276 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 277 ((CCXN) == TIM_CCxN_Disable)) 278 /** 279 * @} 280 */ 281 282 /** @defgroup Break_Input_enable_disable 283 * @{ 284 */ 285 286 #define TIM_Break_Enable ((uint16_t)0x1000) 287 #define TIM_Break_Disable ((uint16_t)0x0000) 288 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 289 ((STATE) == TIM_Break_Disable)) 290 /** 291 * @} 292 */ 293 294 /** @defgroup Break_Polarity 295 * @{ 296 */ 297 298 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 299 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 300 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 301 ((POLARITY) == TIM_BreakPolarity_High)) 302 /** 303 * @} 304 */ 305 306 /** @defgroup TIM_AOE_Bit_Set_Reset 307 * @{ 308 */ 309 310 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 311 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 312 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 313 ((STATE) == TIM_AutomaticOutput_Disable)) 314 /** 315 * @} 316 */ 317 318 /** @defgroup Lock_levels 319 * @{ 320 */ 321 322 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 323 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 324 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 325 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 326 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 327 ((LEVEL) == TIM_LOCKLevel_1) || \ 328 ((LEVEL) == TIM_LOCKLevel_2) || \ 329 ((LEVEL) == TIM_LOCKLevel_3)) 330 /** 331 * @} 332 */ 333 334 /** @defgroup OSSI:_Off-State_Selection_for_Idle_mode_states 335 * @{ 336 */ 337 338 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 339 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 340 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 341 ((STATE) == TIM_OSSIState_Disable)) 342 /** 343 * @} 344 */ 345 346 /** @defgroup OSSR:_Off-State_Selection_for_Run_mode_states 347 * @{ 348 */ 349 350 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 351 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 352 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 353 ((STATE) == TIM_OSSRState_Disable)) 354 /** 355 * @} 356 */ 357 358 /** @defgroup TIM_Output_Compare_Idle_State 359 * @{ 360 */ 361 362 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 363 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 364 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 365 ((STATE) == TIM_OCIdleState_Reset)) 366 /** 367 * @} 368 */ 369 370 /** @defgroup TIM_Output_Compare_N_Idle_State 371 * @{ 372 */ 373 374 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 375 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 376 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 377 ((STATE) == TIM_OCNIdleState_Reset)) 378 /** 379 * @} 380 */ 381 382 /** @defgroup TIM_Input_Capture_Polarity 383 * @{ 384 */ 385 386 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 387 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 388 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 389 ((POLARITY) == TIM_ICPolarity_Falling)) 390 /** 391 * @} 392 */ 393 394 /** @defgroup TIM_Input_Capture_Selection 395 * @{ 396 */ 397 398 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) 399 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) 400 #define TIM_ICSelection_TRC ((uint16_t)0x0003) 401 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 402 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 403 ((SELECTION) == TIM_ICSelection_TRC)) 404 /** 405 * @} 406 */ 407 408 /** @defgroup TIM_Input_Capture_Prescaler 409 * @{ 410 */ 411 412 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) 413 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) 414 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) 415 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) 416 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 417 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 418 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 419 ((PRESCALER) == TIM_ICPSC_DIV8)) 420 /** 421 * @} 422 */ 423 424 /** @defgroup TIM_interrupt_sources 425 * @{ 426 */ 427 428 #define TIM_IT_Update ((uint16_t)0x0001) 429 #define TIM_IT_CC1 ((uint16_t)0x0002) 430 #define TIM_IT_CC2 ((uint16_t)0x0004) 431 #define TIM_IT_CC3 ((uint16_t)0x0008) 432 #define TIM_IT_CC4 ((uint16_t)0x0010) 433 #define TIM_IT_COM ((uint16_t)0x0020) 434 #define TIM_IT_Trigger ((uint16_t)0x0040) 435 #define TIM_IT_Break ((uint16_t)0x0080) 436 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 437 #define IS_TIM_PERIPH_IT(PERIPH, TIM_IT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ 438 (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ 439 (((TIM_IT) & (uint16_t)0xFFA0) == 0x0000) && ((TIM_IT) != 0x0000)) ||\ 440 (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ 441 (((TIM_IT) & (uint16_t)0xFF00) == 0x0000) && ((TIM_IT) != 0x0000)) ||\ 442 (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ 443 (((TIM_IT) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_IT) != 0x0000))) 444 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 445 ((IT) == TIM_IT_CC1) || \ 446 ((IT) == TIM_IT_CC2) || \ 447 ((IT) == TIM_IT_CC3) || \ 448 ((IT) == TIM_IT_CC4) || \ 449 ((IT) == TIM_IT_COM) || \ 450 ((IT) == TIM_IT_Trigger) || \ 451 ((IT) == TIM_IT_Break)) 452 /** 453 * @} 454 */ 455 456 /** @defgroup TIM_DMA_Base_address 457 * @{ 458 */ 459 460 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 461 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 462 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 463 #define TIM_DMABase_DIER ((uint16_t)0x0003) 464 #define TIM_DMABase_SR ((uint16_t)0x0004) 465 #define TIM_DMABase_EGR ((uint16_t)0x0005) 466 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 467 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 468 #define TIM_DMABase_CCER ((uint16_t)0x0008) 469 #define TIM_DMABase_CNT ((uint16_t)0x0009) 470 #define TIM_DMABase_PSC ((uint16_t)0x000A) 471 #define TIM_DMABase_ARR ((uint16_t)0x000B) 472 #define TIM_DMABase_RCR ((uint16_t)0x000C) 473 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 474 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 475 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 476 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 477 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 478 #define TIM_DMABase_DCR ((uint16_t)0x0012) 479 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ 480 ((BASE) == TIM_DMABase_CR2) || \ 481 ((BASE) == TIM_DMABase_SMCR) || \ 482 ((BASE) == TIM_DMABase_DIER) || \ 483 ((BASE) == TIM_DMABase_SR) || \ 484 ((BASE) == TIM_DMABase_EGR) || \ 485 ((BASE) == TIM_DMABase_CCMR1) || \ 486 ((BASE) == TIM_DMABase_CCMR2) || \ 487 ((BASE) == TIM_DMABase_CCER) || \ 488 ((BASE) == TIM_DMABase_CNT) || \ 489 ((BASE) == TIM_DMABase_PSC) || \ 490 ((BASE) == TIM_DMABase_ARR) || \ 491 ((BASE) == TIM_DMABase_RCR) || \ 492 ((BASE) == TIM_DMABase_CCR1) || \ 493 ((BASE) == TIM_DMABase_CCR2) || \ 494 ((BASE) == TIM_DMABase_CCR3) || \ 495 ((BASE) == TIM_DMABase_CCR4) || \ 496 ((BASE) == TIM_DMABase_BDTR) || \ 497 ((BASE) == TIM_DMABase_DCR)) 498 /** 499 * @} 500 */ 501 502 /** @defgroup TIM_DMA_Burst_Length 503 * @{ 504 */ 505 506 #define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) 507 #define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) 508 #define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) 509 #define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) 510 #define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) 511 #define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) 512 #define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) 513 #define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) 514 #define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) 515 #define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) 516 #define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) 517 #define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) 518 #define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) 519 #define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) 520 #define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) 521 #define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) 522 #define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) 523 #define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) 524 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ 525 ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ 526 ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ 527 ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ 528 ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ 529 ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ 530 ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ 531 ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ 532 ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ 533 ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ 534 ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ 535 ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ 536 ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ 537 ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ 538 ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ 539 ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ 540 ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ 541 ((LENGTH) == TIM_DMABurstLength_18Bytes)) 542 /** 543 * @} 544 */ 545 546 /** @defgroup TIM_DMA_sources 547 * @{ 548 */ 549 550 #define TIM_DMA_Update ((uint16_t)0x0100) 551 #define TIM_DMA_CC1 ((uint16_t)0x0200) 552 #define TIM_DMA_CC2 ((uint16_t)0x0400) 553 #define TIM_DMA_CC3 ((uint16_t)0x0800) 554 #define TIM_DMA_CC4 ((uint16_t)0x1000) 555 #define TIM_DMA_COM ((uint16_t)0x2000) 556 #define TIM_DMA_Trigger ((uint16_t)0x4000) 557 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 558 #define IS_TIM_PERIPH_DMA(PERIPH, SOURCE) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ 559 (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ 560 (((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\ 561 (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ 562 (((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) ||\ 563 (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ 564 (((SOURCE) & (uint16_t)0xFEFF) == 0x0000) && ((SOURCE) != 0x0000))) 565 /** 566 * @} 567 */ 568 569 /** @defgroup TIM_External_Trigger_Prescaler 570 * @{ 571 */ 572 573 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 574 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 575 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 576 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 577 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 578 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 579 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 580 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 581 /** 582 * @} 583 */ 584 585 /** @defgroup TIM_Internal_Trigger_Selection 586 * @{ 587 */ 588 589 #define TIM_TS_ITR0 ((uint16_t)0x0000) 590 #define TIM_TS_ITR1 ((uint16_t)0x0010) 591 #define TIM_TS_ITR2 ((uint16_t)0x0020) 592 #define TIM_TS_ITR3 ((uint16_t)0x0030) 593 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 594 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 595 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 596 #define TIM_TS_ETRF ((uint16_t)0x0070) 597 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 598 ((SELECTION) == TIM_TS_ITR1) || \ 599 ((SELECTION) == TIM_TS_ITR2) || \ 600 ((SELECTION) == TIM_TS_ITR3) || \ 601 ((SELECTION) == TIM_TS_TI1F_ED) || \ 602 ((SELECTION) == TIM_TS_TI1FP1) || \ 603 ((SELECTION) == TIM_TS_TI2FP2) || \ 604 ((SELECTION) == TIM_TS_ETRF)) 605 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 606 ((SELECTION) == TIM_TS_ITR1) || \ 607 ((SELECTION) == TIM_TS_ITR2) || \ 608 ((SELECTION) == TIM_TS_ITR3)) 609 /** 610 * @} 611 */ 612 613 /** @defgroup TIM_TIx_External_Clock_Source 614 * @{ 615 */ 616 617 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 618 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 619 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 620 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ 621 ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ 622 ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) 623 /** 624 * @} 625 */ 626 627 /** @defgroup TIM_External_Trigger_Polarity 628 * @{ 629 */ 630 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 631 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 632 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 633 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 634 /** 635 * @} 636 */ 637 638 /** @defgroup TIM_Prescaler_Reload_Mode 639 * @{ 640 */ 641 642 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 643 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 644 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 645 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 646 /** 647 * @} 648 */ 649 650 /** @defgroup TIM_Forced_Action 651 * @{ 652 */ 653 654 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 655 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 656 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 657 ((ACTION) == TIM_ForcedAction_InActive)) 658 /** 659 * @} 660 */ 661 662 /** @defgroup TIM_Encoder_Mode 663 * @{ 664 */ 665 666 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 667 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 668 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 669 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 670 ((MODE) == TIM_EncoderMode_TI2) || \ 671 ((MODE) == TIM_EncoderMode_TI12)) 672 /** 673 * @} 674 */ 675 676 677 /** @defgroup TIM_Event_Source 678 * @{ 679 */ 680 681 #define TIM_EventSource_Update ((uint16_t)0x0001) 682 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 683 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 684 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 685 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 686 #define TIM_EventSource_COM ((uint16_t)0x0020) 687 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 688 #define TIM_EventSource_Break ((uint16_t)0x0080) 689 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 690 #define IS_TIM_PERIPH_EVENT(PERIPH, EVENT) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ 691 (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ 692 (((EVENT) & (uint16_t)0xFFA0) == 0x0000) && ((EVENT) != 0x0000)) ||\ 693 (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ 694 (((EVENT) & (uint16_t)0xFF00) == 0x0000) && ((EVENT) != 0x0000)) ||\ 695 (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ 696 (((EVENT) & (uint16_t)0xFFFE) == 0x0000) && ((EVENT) != 0x0000))) 697 /** 698 * @} 699 */ 700 701 /** @defgroup TIM_Update_Source 702 * @{ 703 */ 704 705 #define TIM_UpdateSource_Global ((uint16_t)0x0000) 706 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) 707 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 708 ((SOURCE) == TIM_UpdateSource_Regular)) 709 /** 710 * @} 711 */ 712 713 /** @defgroup TIM_Ouput_Compare_Preload_State 714 * @{ 715 */ 716 717 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 718 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 719 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 720 ((STATE) == TIM_OCPreload_Disable)) 721 /** 722 * @} 723 */ 724 725 /** @defgroup TIM_Ouput_Compare_Fast_State 726 * @{ 727 */ 728 729 #define TIM_OCFast_Enable ((uint16_t)0x0004) 730 #define TIM_OCFast_Disable ((uint16_t)0x0000) 731 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 732 ((STATE) == TIM_OCFast_Disable)) 733 734 /** 735 * @} 736 */ 737 738 /** @defgroup TIM_Ouput_Compare_Clear_State 739 * @{ 740 */ 741 742 #define TIM_OCClear_Enable ((uint16_t)0x0080) 743 #define TIM_OCClear_Disable ((uint16_t)0x0000) 744 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 745 ((STATE) == TIM_OCClear_Disable)) 746 /** 747 * @} 748 */ 749 750 /** @defgroup TIM_Trigger_Output_Source 751 * @{ 752 */ 753 754 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 755 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 756 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 757 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 758 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 759 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 760 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 761 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 762 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 763 ((SOURCE) == TIM_TRGOSource_Enable) || \ 764 ((SOURCE) == TIM_TRGOSource_Update) || \ 765 ((SOURCE) == TIM_TRGOSource_OC1) || \ 766 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 767 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 768 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 769 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 770 #define IS_TIM_PERIPH_TRGO(PERIPH, TRGO) (((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 771 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 772 (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \ 773 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 774 ((TRGO) == TIM_TRGOSource_Reset)) ||\ 775 ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 776 (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \ 777 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 778 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 779 ((TRGO) == TIM_TRGOSource_Enable)) ||\ 780 ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 781 (((*(uint32_t*)&(PERIPH)) == TIM6_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM7_BASE))|| \ 782 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 783 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 784 ((TRGO) == TIM_TRGOSource_Update)) ||\ 785 ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 786 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 787 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 788 ((TRGO) == TIM_TRGOSource_OC1)) ||\ 789 ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 790 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 791 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 792 ((TRGO) == TIM_TRGOSource_OC1Ref)) ||\ 793 ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 794 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 795 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 796 ((TRGO) == TIM_TRGOSource_OC2Ref)) ||\ 797 ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 798 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 799 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 800 ((TRGO) == TIM_TRGOSource_OC3Ref)) ||\ 801 ((((*(uint32_t*)&(PERIPH)) == TIM2_BASE)||(((*(uint32_t*)&(PERIPH)) == TIM1_BASE))||\ 802 (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM4_BASE))|| \ 803 (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))||(((*(uint32_t*)&(PERIPH)) == TIM8_BASE))) && \ 804 ((TRGO) == TIM_TRGOSource_OC4Ref))) 805 /** 806 * @} 807 */ 808 809 /** @defgroup TIM_Slave_Mode 810 * @{ 811 */ 812 813 #define TIM_SlaveMode_Reset ((uint16_t)0x0004) 814 #define TIM_SlaveMode_Gated ((uint16_t)0x0005) 815 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) 816 #define TIM_SlaveMode_External1 ((uint16_t)0x0007) 817 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 818 ((MODE) == TIM_SlaveMode_Gated) || \ 819 ((MODE) == TIM_SlaveMode_Trigger) || \ 820 ((MODE) == TIM_SlaveMode_External1)) 821 /** 822 * @} 823 */ 824 825 /** @defgroup TIM_Master_Slave_Mode 826 * @{ 827 */ 828 829 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 830 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 831 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 832 ((STATE) == TIM_MasterSlaveMode_Disable)) 833 /** 834 * @} 835 */ 836 837 /** @defgroup TIM_Flags 838 * @{ 839 */ 840 841 #define TIM_FLAG_Update ((uint16_t)0x0001) 842 #define TIM_FLAG_CC1 ((uint16_t)0x0002) 843 #define TIM_FLAG_CC2 ((uint16_t)0x0004) 844 #define TIM_FLAG_CC3 ((uint16_t)0x0008) 845 #define TIM_FLAG_CC4 ((uint16_t)0x0010) 846 #define TIM_FLAG_COM ((uint16_t)0x0020) 847 #define TIM_FLAG_Trigger ((uint16_t)0x0040) 848 #define TIM_FLAG_Break ((uint16_t)0x0080) 849 #define TIM_FLAG_CC1OF ((uint16_t)0x0200) 850 #define TIM_FLAG_CC2OF ((uint16_t)0x0400) 851 #define TIM_FLAG_CC3OF ((uint16_t)0x0800) 852 #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 853 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 854 ((FLAG) == TIM_FLAG_CC1) || \ 855 ((FLAG) == TIM_FLAG_CC2) || \ 856 ((FLAG) == TIM_FLAG_CC3) || \ 857 ((FLAG) == TIM_FLAG_CC4) || \ 858 ((FLAG) == TIM_FLAG_COM) || \ 859 ((FLAG) == TIM_FLAG_Trigger) || \ 860 ((FLAG) == TIM_FLAG_Break) || \ 861 ((FLAG) == TIM_FLAG_CC1OF) || \ 862 ((FLAG) == TIM_FLAG_CC2OF) || \ 863 ((FLAG) == TIM_FLAG_CC3OF) || \ 864 ((FLAG) == TIM_FLAG_CC4OF)) 865 #define IS_TIM_CLEAR_FLAG(PERIPH, TIM_FLAG) ((((((*(uint32_t*)&(PERIPH)) == TIM2_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM3_BASE))||\ 866 (((*(uint32_t*)&(PERIPH)) == TIM4_BASE)) || (((*(uint32_t*)&(PERIPH)) == TIM5_BASE))))&& \ 867 (((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\ 868 (((((*(uint32_t*)&(PERIPH)) == TIM1_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM8_BASE))))&& \ 869 (((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) ||\ 870 (((((*(uint32_t*)&(PERIPH)) == TIM6_BASE) || (((*(uint32_t*)&(PERIPH)) == TIM7_BASE))))&& \ 871 (((TIM_FLAG) & (uint16_t)0xFFFE) == 0x0000) && ((TIM_FLAG) != 0x0000))) 872 #define IS_TIM_PERIPH_FLAG(PERIPH, TIM_FLAG) (((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) ||\ 873 ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \ 874 ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\ 875 (((TIM_FLAG) == TIM_FLAG_CC1) || ((TIM_FLAG) == TIM_FLAG_CC2) ||\ 876 ((TIM_FLAG) == TIM_FLAG_CC3) || ((TIM_FLAG) == TIM_FLAG_CC4) || \ 877 ((TIM_FLAG) == TIM_FLAG_Trigger))) ||\ 878 ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ 879 ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) ||\ 880 ((*(uint32_t*)&(PERIPH))==TIM1_BASE)|| ((*(uint32_t*)&(PERIPH))==TIM8_BASE) || \ 881 ((*(uint32_t*)&(PERIPH))==TIM7_BASE) || ((*(uint32_t*)&(PERIPH))==TIM6_BASE)) && \ 882 (((TIM_FLAG) == TIM_FLAG_Update))) ||\ 883 ((((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM8_BASE)) &&\ 884 (((TIM_FLAG) == TIM_FLAG_COM) || ((TIM_FLAG) == TIM_FLAG_Break))) ||\ 885 ((((*(uint32_t*)&(PERIPH))==TIM2_BASE) || ((*(uint32_t*)&(PERIPH)) == TIM3_BASE) || \ 886 ((*(uint32_t*)&(PERIPH)) == TIM4_BASE) || ((*(uint32_t*)&(PERIPH))==TIM5_BASE) || \ 887 ((*(uint32_t*)&(PERIPH))==TIM1_BASE) || ((*(uint32_t*)&(PERIPH))==TIM8_BASE)) &&\ 888 (((TIM_FLAG) == TIM_FLAG_CC1OF) || ((TIM_FLAG) == TIM_FLAG_CC2OF) ||\ 889 ((TIM_FLAG) == TIM_FLAG_CC3OF) || ((TIM_FLAG) == TIM_FLAG_CC4OF)))) 890 891 /** 892 * @} 893 */ 894 895 /** @defgroup TIM_Input_Capture_Filer_Value 896 * @{ 897 */ 898 899 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 900 /** 901 * @} 902 */ 903 904 /** @defgroup TIM_External_Trigger_Filter 905 * @{ 906 */ 907 908 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 909 /** 910 * @} 911 */ 912 913 /** 914 * @} 915 */ 916 917 /** @defgroup TIM_Exported_Macros 918 * @{ 919 */ 920 921 /** 922 * @} 923 */ 924 925 /** @defgroup TIM_Exported_Functions 926 * @{ 927 */ 928 929 void TIM_DeInit(TIM_TypeDef* TIMx); 930 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 931 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 932 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 933 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 934 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 935 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 936 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 937 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 938 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 939 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); 940 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); 941 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); 942 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 943 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); 944 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); 945 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); 946 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 947 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 948 void TIM_InternalClockConfig(TIM_TypeDef* TIMx); 949 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 950 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 951 uint16_t TIM_ICPolarity, uint16_t ICFilter); 952 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 953 uint16_t ExtTRGFilter); 954 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 955 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 956 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 957 uint16_t ExtTRGFilter); 958 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 959 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); 960 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 961 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 962 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 963 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 964 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 965 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 966 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 967 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 968 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); 969 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); 970 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); 971 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 972 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 973 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 974 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 975 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 976 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 977 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 978 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 979 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 980 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 981 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 982 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 983 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 984 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 985 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 986 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 987 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 988 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 989 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 990 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 991 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 992 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); 993 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 994 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); 995 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); 996 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); 997 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 998 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 999 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 1000 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); 1001 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); 1002 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); 1003 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); 1004 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); 1005 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); 1006 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1007 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1008 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1009 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1010 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); 1011 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); 1012 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); 1013 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); 1014 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); 1015 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); 1016 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); 1017 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 1018 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 1019 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1020 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1021 1022 #endif /*__HAL_TIM_H */ 1023 /** 1024 * @} 1025 */ 1026 1027 /** 1028 * @} 1029 */ 1030 1031 /** 1032 * @} 1033 */ 1034 1035 /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/ 1036 1037