1 /**
2 ******************************************************************************
3 * @file HAL_dma.c
4 * @author AE Team
5 * @version V1.0.0
6 * @date 28/7/2017
7 * @brief This file provides all the DMA firmware functions.
8 ******************************************************************************
9 * @copy
10 *
11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
13 * TIME. AS A RESULT, MindMotion SHALL NOT BE HELD LIABLE FOR ANY
14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
17 *
18 * <h2><center>© COPYRIGHT 2017 MindMotion</center></h2>
19 */
20
21 /* Includes ------------------------------------------------------------------*/
22 #include "HAL_dma.h"
23
24
25 /** @addtogroup StdPeriph_Driver
26 * @{
27 */
28
29 /** @defgroup DMA
30 * @brief DMA driver modules
31 * @{
32 */
33
34 /** @defgroup DMA_Private_TypesDefinitions
35 * @{
36 */
37 /**
38 * @}
39 */
40
41 /** @defgroup DMA_Private_Defines
42 * @{
43 */
44
45 /* DMA ENABLE mask */
46 #define CCR_ENABLE_Set ((uint32_t)0x00000001)
47 #define CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE)
48
49 /* DMA1 Channelx interrupt pending bit masks */
50 #define DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F)
51 #define DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0)
52 #define DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00)
53 #define DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000)
54 #define DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000)
55 #define DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000)
56 #define DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000)
57
58
59
60
61
62
63 /* DMA registers Masks */
64 #define CCR_CLEAR_Mask ((uint32_t)0xFFFF800F)
65
66 /**
67 * @}
68 */
69
70 /** @defgroup DMA_Private_Macros
71 * @{
72 */
73
74 /**
75 * @}
76 */
77
78 /** @defgroup DMA_Private_Variables
79 * @{
80 */
81
82 /**
83 * @}
84 */
85
86 /** @defgroup DMA_Private_FunctionPrototypes
87 * @{
88 */
89
90 /**
91 * @}
92 */
93
94 /** @defgroup DMA_Private_Functions
95 * @{
96 */
97
98 /**
99 * @brief Deinitializes the DMAy Channelx registers to their default reset
100 * values.
101 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
102 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
103 * DMA Channel.
104 * @retval : None
105 */
DMA_DeInit(DMA_Channel_TypeDef * DMAy_Channelx)106 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
107 {
108 /* Check the parameters */
109 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
110 /* Disable the selected DMAy Channelx */
111 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
112 /* Reset DMAy Channelx control register */
113 DMAy_Channelx->CCR = 0;
114
115 /* Reset DMAy Channelx remaining bytes register */
116 DMAy_Channelx->CNDTR = 0;
117
118 /* Reset DMAy Channelx peripheral address register */
119 DMAy_Channelx->CPAR = 0;
120
121 /* Reset DMAy Channelx memory address register */
122 DMAy_Channelx->CMAR = 0;
123 switch (*(uint32_t*)&DMAy_Channelx)
124 {
125 case DMA1_Channel1_BASE:
126 /* Reset interrupt pending bits for DMA1 Channel1 */
127 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
128 break;
129 case DMA1_Channel2_BASE:
130 /* Reset interrupt pending bits for DMA1 Channel2 */
131 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
132 break;
133 case DMA1_Channel3_BASE:
134 /* Reset interrupt pending bits for DMA1 Channel3 */
135 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
136 break;
137 case DMA1_Channel4_BASE:
138 /* Reset interrupt pending bits for DMA1 Channel4 */
139 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
140 break;
141 case DMA1_Channel5_BASE:
142 /* Reset interrupt pending bits for DMA1 Channel5 */
143 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
144 break;
145 case DMA1_Channel6_BASE:
146 /* Reset interrupt pending bits for DMA1 Channel6 */
147 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
148 break;
149 case DMA1_Channel7_BASE:
150 /* Reset interrupt pending bits for DMA1 Channel7 */
151 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
152 break;
153
154 default:
155 break;
156 }
157 }
158
159 /**
160 * @brief Initializes the DMAy Channelx according to the specified
161 * parameters in the DMA_InitStruct.
162 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
163 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
164 * DMA Channel.
165 * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
166 * contains the configuration information for the specified
167 * DMA Channel.
168 * @retval : None
169 */
DMA_Init(DMA_Channel_TypeDef * DMAy_Channelx,DMA_InitTypeDef * DMA_InitStruct)170 void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
171 {
172 uint32_t tmpreg = 0;
173 /* Check the parameters */
174 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
175 assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
176 assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
177 assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
178 assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
179 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
180 assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
181 assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
182 assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
183 assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
184 /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
185 /* Get the DMAy_Channelx CCR value */
186 tmpreg = DMAy_Channelx->CCR;
187 /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
188 tmpreg &= CCR_CLEAR_Mask;
189 /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
190 /* Set DIR bit according to DMA_DIR value */
191 /* Set CIRC bit according to DMA_Mode value */
192 /* Set PINC bit according to DMA_PeripheralInc value */
193 /* Set MINC bit according to DMA_MemoryInc value */
194 /* Set PSIZE bits according to DMA_PeripheralDataSize value */
195 /* Set MSIZE bits according to DMA_MemoryDataSize value */
196 /* Set PL bits according to DMA_Priority value */
197 /* Set the MEM2MEM bit according to DMA_M2M value */
198 tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
199 DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
200 DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
201 DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
202 /* Write to DMAy Channelx CCR */
203 DMAy_Channelx->CCR = tmpreg;
204 /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
205 /* Write to DMAy Channelx CNDTR */
206 DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
207 /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
208 /* Write to DMAy Channelx CPAR */
209 DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
210 /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
211 /* Write to DMAy Channelx CMAR */
212 DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
213 }
214
215 /**
216 * @brief Fills each DMA_InitStruct member with its default value.
217 * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure
218 * which will be initialized.
219 * @retval : None
220 */
DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct)221 void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
222 {
223 /*-------------- Reset DMA init structure parameters values ------------------*/
224 /* Initialize the DMA_PeripheralBaseAddr member */
225 DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
226 /* Initialize the DMA_MemoryBaseAddr member */
227 DMA_InitStruct->DMA_MemoryBaseAddr = 0;
228 /* Initialize the DMA_DIR member */
229 DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
230 /* Initialize the DMA_BufferSize member */
231 DMA_InitStruct->DMA_BufferSize = 0;
232 /* Initialize the DMA_PeripheralInc member */
233 DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
234 /* Initialize the DMA_MemoryInc member */
235 DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
236 /* Initialize the DMA_PeripheralDataSize member */
237 DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
238 /* Initialize the DMA_MemoryDataSize member */
239 DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
240 /* Initialize the DMA_Mode member */
241 DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
242 /* Initialize the DMA_Priority member */
243 DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
244 /* Initialize the DMA_M2M member */
245 DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
246 }
247
248 /**
249 * @brief Enables or disables the specified DMAy Channelx.
250 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
251 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
252 * DMA Channel.
253 * @param NewState: new state of the DMAy Channelx.
254 * This parameter can be: ENABLE or DISABLE.
255 * @retval : None
256 */
DMA_Cmd(DMA_Channel_TypeDef * DMAy_Channelx,FunctionalState NewState)257 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
258 {
259 /* Check the parameters */
260 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
261 assert_param(IS_FUNCTIONAL_STATE(NewState));
262 if (NewState != DISABLE)
263 {
264 /* Enable the selected DMAy Channelx */
265 DMAy_Channelx->CCR |= CCR_ENABLE_Set;
266 }
267 else
268 {
269 /* Disable the selected DMAy Channelx */
270 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
271 }
272 }
273
274 /**
275 * @brief Enables or disables the specified DMAy Channelx interrupts.
276 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
277 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
278 * DMA Channel.
279 * @param DMA_IT: specifies the DMA interrupts sources to be enabled
280 * or disabled.
281 * This parameter can be any combination of the following values:
282 * @arg DMA_IT_TC: Transfer complete interrupt mask
283 * @arg DMA_IT_HT: Half transfer interrupt mask
284 * @arg DMA_IT_TE: Transfer error interrupt mask
285 * @param NewState: new state of the specified DMA interrupts.
286 * This parameter can be: ENABLE or DISABLE.
287 * @retval : None
288 */
DMA_ITConfig(DMA_Channel_TypeDef * DMAy_Channelx,uint32_t DMA_IT,FunctionalState NewState)289 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
290 {
291 /* Check the parameters */
292 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
293 assert_param(IS_DMA_CONFIG_IT(DMA_IT));
294 assert_param(IS_FUNCTIONAL_STATE(NewState));
295 if (NewState != DISABLE)
296 {
297 /* Enable the selected DMA interrupts */
298 DMAy_Channelx->CCR |= DMA_IT;
299 }
300 else
301 {
302 /* Disable the selected DMA interrupts */
303 DMAy_Channelx->CCR &= ~DMA_IT;
304 }
305 }
306
307 /**
308 * @brief Returns the number of remaining data units in the current
309 * DMAy Channelx transfer.
310 * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
311 * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the
312 * DMA Channel.
313 * @retval : The number of remaining data units in the current DMAy Channelx
314 * transfer.
315 */
DMA_GetCurrDataCounter(DMA_Channel_TypeDef * DMAy_Channelx)316 uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
317 {
318 /* Check the parameters */
319 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
320 /* Return the number of remaining data units for DMAy Channelx */
321 return ((uint16_t)(DMAy_Channelx->CNDTR));
322 }
323
324 /**
325 * @brief Checks whether the specified DMAy Channelx flag is set or not.
326 * @param DMA_FLAG: specifies the flag to check.
327 * This parameter can be one of the following values:
328 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
329 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
330 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
331 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
332 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
333 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
334 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
335 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
336 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
337 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
338 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
339 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
340 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
341 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
342 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
343 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
344 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
345 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
346 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
347 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
348 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
349 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
350 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
351 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
352 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
353 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
354 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
355 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
356 * @retval : The new state of DMA_FLAG (SET or RESET).
357 */
DMA_GetFlagStatus(uint32_t DMA_FLAG)358 FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
359 {
360 FlagStatus bitstatus = RESET;
361 uint32_t tmpreg = 0;
362 /* Check the parameters */
363 assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
364
365 /* Get DMA1 ISR register value */
366 tmpreg = DMA1->ISR ;
367
368 /* Check the status of the specified DMA flag */
369 if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
370 {
371 /* DMA_FLAG is set */
372 bitstatus = SET;
373 }
374 else
375 {
376 /* DMA_FLAG is reset */
377 bitstatus = RESET;
378 }
379
380 /* Return the DMA_FLAG status */
381 return bitstatus;
382 }
383
384 /**
385 * @brief Clears the DMAy Channelx's pending flags.
386 * @param DMA_FLAG: specifies the flag to clear.
387 * This parameter can be any combination (for the same DMA) of
388 * the following values:
389 * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
390 * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
391 * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
392 * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
393 * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
394 * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
395 * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
396 * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
397 * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
398 * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
399 * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
400 * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
401 * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
402 * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
403 * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
404 * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
405 * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
406 * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
407 * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
408 * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
409 * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
410 * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
411 * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
412 * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
413 * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
414 * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
415 * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
416 * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
417 * @retval : None
418 */
DMA_ClearFlag(uint32_t DMA_FLAG)419 void DMA_ClearFlag(uint32_t DMA_FLAG)
420 {
421 /* Check the parameters */
422 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
423
424 /* Clear the selected DMA flags */
425 DMA1->IFCR = DMA_FLAG;
426 }
427
428 /**
429 * @brief Checks whether the specified DMAy Channelx interrupt has
430 * occurred or not.
431 * @param DMA_IT: specifies the DMA interrupt source to check.
432 * This parameter can be one of the following values:
433 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
434 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
435 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
436 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
437 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
438 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
439 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
440 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
441 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
442 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
443 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
444 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
445 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
446 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
447 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
448 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
449 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
450 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
451 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
452 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
453 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
454 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
455 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
456 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
457 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
458 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
459 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
460 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
461 * @retval : The new state of DMA_IT (SET or RESET).
462 */
DMA_GetITStatus(uint32_t DMA_IT)463 ITStatus DMA_GetITStatus(uint32_t DMA_IT)
464 {
465 ITStatus bitstatus = RESET;
466 uint32_t tmpreg = 0;
467 /* Check the parameters */
468 assert_param(IS_DMA_GET_IT(DMA_IT));
469
470 /* Get DMA1 ISR register value */
471 tmpreg = DMA1->ISR ;
472
473 /* Check the status of the specified DMA interrupt */
474 if ((tmpreg & DMA_IT) != (uint32_t)RESET)
475 {
476 /* DMA_IT is set */
477 bitstatus = SET;
478 }
479 else
480 {
481 /* DMA_IT is reset */
482 bitstatus = RESET;
483 }
484 /* Return the DMA_IT status */
485 return bitstatus;
486 }
487
488 /**
489 * @brief Clears the DMAy Channelx's interrupt pending bits.
490 * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
491 * This parameter can be any combination (for the same DMA) of
492 * the following values:
493 * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
494 * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
495 * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
496 * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
497 * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
498 * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
499 * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
500 * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
501 * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
502 * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
503 * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
504 * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
505 * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
506 * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
507 * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
508 * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
509 * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
510 * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
511 * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
512 * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
513 * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
514 * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
515 * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
516 * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
517 * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
518 * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
519 * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
520 * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
521 * @retval : None
522 */
DMA_ClearITPendingBit(uint32_t DMA_IT)523 void DMA_ClearITPendingBit(uint32_t DMA_IT)
524 {
525 /* Check the parameters */
526 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
527
528 /* Clear the selected DMA interrupt pending bits */
529 DMA1->IFCR = DMA_IT;
530
531 }
532
533 /**
534 * @}
535 */
536
537 /**
538 * @}
539 */
540
541 /**
542 * @}
543 */
544
545 /*-------------------------(C) COPYRIGHT 2017 MindMotion ----------------------*/
546